Sign in
Search fpga-cpu
Subscribe to fpga-cpu
fpga-cpu by Keywords
Altera | CISCifying | IDE | ISA | Java | JHDL | JTAG | LBU | MicroBlaze | PAR | PCI | RISC | SoC | Spartan | Transputers | Verilog | VHDL | Virtex | VLIW | WebPack | Xilinx | Xsoc | YARD-1A
Discussion Groups
Discussion Groups | FPGA-CPU | Re: 6502 project
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
6502 project - rtfinch35 - Dec 24 13:50:00 2001
|
Frustrated: My 6502 project is so close to working, but it driving me up the wall. I have it displaying a message on screen via a text vga interface. However, branches aren't working. They don't branch. I displayed the flags on the screen and they change, also the "taken" signal changes, however the branch never branches. Also everything works a-okay in ModelSim. I don't think it's a timing thing because I've tried running the cpu at speeds between 3 and 25 MHz and always get the same results. I tried changing the synthesis options - same results. (I wish there was an option to turn off all optimizations). I think I have to build a simple logic analyzer to figure this one out :( Rob |
|
|
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: 6502 project - Ed Corter - Dec 24 14:29:00 2001
|
Try the ILA... Integrated Logic Analyser, if you need help making it work, I will help. I have successfully done it. but not by following xilinx's instructions, I wrote my own set for easier use. Ed --------------------------------- |
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: 6502 project - Eric Werness - Dec 24 14:45:00 2001
|
Couple of things you might try. 1. If you think that the simulator isn't working up to spec, you could try running the verilog on another simulator (Icarus, veriwell, etc) 2. You might try a post-P&R simulation model for model-sim. ~Eric rtfinch35 wrote: > Frustrated: My 6502 project is so close to working, but it driving me > up the wall. I have it displaying a message on screen via a text vga > interface. However, branches aren't working. They don't branch. I > displayed the flags on the screen and they change, also the "taken" > signal changes, however the branch never branches. Also everything > works a-okay in ModelSim. I don't think it's a timing thing because > I've tried running the cpu at speeds between 3 and 25 MHz and always > get the same results. I tried changing the synthesis options - same > results. (I wish there was an option to turn off all optimizations). > I think I have to build a simple logic analyzer to figure this one > out :( > > Rob > > To post a message, send it to: > To unsubscribe, send a blank message to: |
|
|
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: 6502 project - Ed Corter - Dec 24 14:51:00 2001
|
also another synthesis tool, I have had designs fail when changing from one tool to another, If you want I can use FPGA express or next week Synplicity SynplifyPro ( i am gettign a 2 week eval for work ) and I will send you the edif's Ed --------------------------------- |
|
|
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: 6502 project - rtfinch35 - Dec 24 18:52:00 2001
|
Merry, Merry, Merry, Christmas! I have figured out the branch bug. I wasn't simulating the same code in ModelSim that I was trying to implement. Once I did that, the bug was obvious. I now have the cpu echoing back characters sent to it via my pc. This is good because I can now write a simple bootstrap loader with better processor assurance testing. > also another synthesis tool, I have had designs fail when changing from one tool to another, I can' really switch tools. I'm developing with Webpack and I want to keep development in Webpack if at all possible. Unless the tools are "free" and widely available, I don't want to waste time learning them. I try not to look at things I can't afford, it saves a lot of heartache. Rob http://www.birdcomputer.ca/ |
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )