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Discussion Groups | FPGA-CPU | verilog vs Logiblox

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

verilog vs Logiblox - Rob Finch - Aug 16 6:41:00 2000

I'm in the process of designing my very own mpu and I noticed that if
I create an adder / subtracter using LogiBlox (Xilinx F1.5 software)
it takes up alot less 4-LUTs than using Verilog code does. I'm
assuming this is because LogiBlox knows about the dedicated carry
chain and maybe the Verilog compiler doesn't ? Is there a way in
Verilog code to tell it to generate the adder more (space)
efficiently ?
How portable is the stuff generated by LogiBlox ?

PS. What is the polarity of the add / sub signal generated by
LogiBlox ? High for add and low for sub ? or vice versa ? I'm
assuming the first thing listed is the active high one, but ....

Thanks
Rob





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Re: verilog vs Logiblox - Arrigo Benedetti - Aug 16 17:34:00 2000

"Rob Finch" <> writes:

> I'm in the process of designing my very own mpu and I noticed that if
> I create an adder / subtracter using LogiBlox (Xilinx F1.5 software)
> it takes up alot less 4-LUTs than using Verilog code does. I'm
> assuming this is because LogiBlox knows about the dedicated carry
> chain and maybe the Verilog compiler doesn't ? Is there a way in
> Verilog code to tell it to generate the adder more (space)
> efficiently ?
> How portable is the stuff generated by LogiBlox ? Any modern verilog/vhdl compiler should infer an adder with the dedicated
carry chain. Are you sure the problem is not somewhere else?

good luck,

-Arrigo





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RE: verilog vs Logiblox - Jan Gray - Aug 17 19:30:00 2000

> I'm in the process of designing my very own mpu and I noticed that if
> I create an adder / subtracter using LogiBlox (Xilinx F1.5 software)
> it takes up alot less 4-LUTs than using Verilog code does. I'm
> assuming this is because LogiBlox knows about the dedicated carry
> chain and maybe the Verilog compiler doesn't ? Is there a way in
> Verilog code to tell it to generate the adder more (space)
> efficiently ?

That may depend upon the Verilog synthesizer and exactly how you wrote your
adder/subtractor. When I did the XSOC/xr16 schematics->Verilog conversion,
I spent quite a while "pushing on a rope" to discover what I had to feed
FPGA Express to generate essentially an ADSU16, e.g. an 8 CLB tall
adder/subtractor with carry-in, carry-out, and overflow. If I didn't get it
just right, FPGA Express would instead generate an adder and a subtractor
and a mux. Maybe that is happening to you. Did you code your
adder/subtractor as I did (see below), and are you using FPGA Express?

/* Excerpted from xsoc/xsocv/datapath.v */
assign a15 = a[15];
reg ign;
reg co0;
always @(a or b or add or ci) begin
if (add) begin
{co0,sum,ign} = {a,ci} + {b,1'b1};
co = co0;
end
else begin
{co0,sum,ign} = {a,ci} - {b,1'b1};
co = ~co0;
end
z = sum == 0;
n = sum[15];
// sum[15] = a[15] ^ b[15] ^ c15 <===> c15 = sum[15] ^ a[15] ^ b[15]
v = co0 ^ sum[15] ^ a[15] ^ b[15];
end > How portable is the stuff generated by LogiBlox ?

I assume it is not portable except to the device family for which you have
it configured.

> PS. What is the polarity of the add / sub signal generated by
> LogiBlox ? High for add and low for sub ? or vice versa ? I'm
> assuming the first thing listed is the active high one, but ....

Sorry, I don't remember.

Jan Gray
Gray Research LLC



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