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Discussion Groups | FPGA-CPU | RE: Found link to Veriwell executable

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

Found link to Veriwell executable - Arrigo Benedetti - Aug 17 2:32:00 2000



Just in case this is useful to anybody ...

http://www.ee.ed.ac.uk/~me99wrt/gateway/veriwell.exe

Best,

-Arrigo


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Re: Found link to Veriwell executable - Arrigo Benedetti - Aug 17 16:57:00 2000

Arrigo Benedetti <> writes:

> Just in case this is useful to anybody ...
>
> http://www.ee.ed.ac.uk/~me99wrt/gateway/veriwell.exe Oops... this executable does not work, however this one does:

http://www.engr.usask.ca/classes/EE/451/software/veriwell.exe

Cheers,

-Arrigo


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RE: Found link to Veriwell executable - Jan Gray - Aug 17 17:17:00 2000

Thank you, very helpful. Well, I was about to push this up to the web site:

"
Veriwell sightings

In the XSOC Getting Started Guide, I lament that I was unable to find a copy
of the Veriwell free Verilog simulator on the web now that wellspring.com is
no more. Fortunately Arrigo Benedetti found this _link_ (Veriwell 2.1.1),
and a few minutes with Google produced this _link_ (Veriwell 2.1.7). (Of
course, Gray Research LLC cannot vouch for the provenance of these
executables, which may carry viruses, etc., use at your own risk.)

Either version will run the xsocv/xsoc.prj Verilog XSOC/xr16 testbench in
the XSOC project kit. Quoting from 2.1.7 version's README.1ST:

Copy Policy

SynaptiCAD encourages the unlimited copying of VeriWell! VeriWell is
copyrighted, yet freely distributable. Unlike most other software that is
protected by a hardware key, VeriWell WILL run without one. We want to make
Verilog HDL accessible to anyone who wants to use Verilog for whatever
reason -- evaluation, education, training, etc.

The Concept of "Free" and "Registered"

VeriWell runs in one of two modes: "free" and "registered". In the "free"
mode, VeriWell enables all features and functions, but limits the size of
the input model to a total of approximately 1000 lines. This limit was
selected by University Professors and Verilog users. This should give the
user enough capacity to run small-to-medium-sized models for coursework,
training, evaluation, and even some commercial applications.

Thanks to the authors of this useful software for their beneficence.
"

I *thought* I had installed both versions and tried them out, but as you
indicate otherwise, I'll drop the reference to the 2.1.1 version at
ee.ed.ac.uk and just keep the USask one.

Thank you for your help!

Jan Gray
Gray Research LLC



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