This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
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I got the basic design verilog for a simple mpu (24 bit, which works quite nicely) done and I'd like to simulate it, but I figure it to be between 1200-1500 lines of verilog. IE. I probably won't be able to use the veriwell simulator with the 1k limit. I'm willing to pay a small amount (<$100) for a simulator, does anyone have any suggestions ? Thanks Rob |
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http://www.icarus.com/eda/verilog/ (Linux) --Mike On Fri, 18 Aug 2000, you wrote: > I got the basic design verilog for a simple mpu (24 bit, which works > quite nicely) done and I'd like to simulate it, but I figure it to be > between 1200-1500 lines of verilog. IE. I probably won't be able to > use the veriwell simulator with the 1k limit. > I'm willing to pay a small amount (<$100) for a simulator, does > anyone have any suggestions ? > > Thanks > Rob > > To Post a message, send it to: > > To Unsubscribe, send a blank message to: |