--- m68HC11@m68H... wrote:
    From: "teejsd" <tmjorenby@tmjo...>
>     OK I am my own answer.....for anyone who's using the BUS_Port of 
> the CME11E9-EVBU.  As the SMALL bit of documentation on this port 
> says, it is for attaching off-board devices to the E9 that can then
> be read/written through the appropriate "peripheral area" mapped
> memory locations ($B580-$B5FF).
...
>     I still have no data on the actual timing of the CS'/OE'/WR' 
> strobes, but I can say they are compatible with my off-board TTL
> chip, because I am successfully reading and writing it using this 
> port....or, as my ex-lab instructor was saying about interfacing my 
> TTL device with this port "It's a device.  Of course it's going to 
> work.  They set it up so any idiot--I mean user--can use it."  He was
> so right.

I, for one, appreciate you taking the time to provide a follow-up on
this issue, even though it is an answer to your own question.  Not only
will others that are using this board (made by Axiom, right?)
appreciate your efforts, it also indicates to the Old Farts on this
list that you are willing to do a bit of your own legwork to resolve an
issue.  Doing so is bound to gain you some respect from the
aforementioned group, who will lkely be more inclined to assisting you
with any other problems you are having.

This is not to say that questions from beginners are unwelcome; we all
realize that the learning curve on topics such as those discussed here
is steep.  However, showing some initiative for solving one's own
problems is an indication to the rest of us that any time spent
responding to (your) future inquiries will not be wasted.

Concerning your question regarding timing specifics for the 'bus port',
you can probably deduce this with some degree of accuracy if you have a
schematic of your board handy.  It should be part of the documentation
that comes with the board, or, if you don't have it, you should be able
to get (download) it from Axiom Manufacturing.  You need to consider
the delays of the logic elements that form the address decoding logic. 
Odds are that a 74HC138 is one of the key components of the decode
logic, which has a tPD of 30 nS or so, as I recall.  Any logic, such as
NAND gates or PLDs, that is 'in front of' the '138 will add to the
total tPD.

If you can dig up a schematic for your board I can probably help you
guesstimate the worst-case tPD (propogation delay) for the signals you
are interested in.