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Hello, I have started exploring LPC210x. Would anyone comment please, based on their experience, on the following (that striked me)? Quote, from the latest data sheet(2003-10-02)- MAMTIM: " Flash access time is suggested to be 2 CCLKs, while in systems with system clock faster than 40 MHz, 3 CCLKs are proposed." 1. How *realistic* is to expect LPC210x to run 60MHz with 3 fetch cycles? 2. Is the performance better than with 20MHz and 1 fetch cycle? Mathematically it appears identical (60/3=20/1). 3. What is really the *worst* case for INT latency? 3.1 Best case? ...[700ns given by ARM DDI0234A_7TDMIS_R4.pdf, pg 2-26) @ 40 MHz]. What it would be on LPC210x MCU, at 20MHz/60MHz as mentioned above? Thank you. Best regards. --lynx

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> 1. How *realistic* is to expect LPC210x to run 60MHz with 3 fetch cycles? > 2. Is the performance better than with 20MHz and 1 fetch cycle? > Mathematically it appears identical (60/3=20/1). What MAM unit does is, it gets 128bits from flash at once, so that is good for 4cycles (4*32=128). So basicly CPU runs at 60MHz and fetches 128bits at once from flash at 20MHz(considering 3 fetch cycles). This is ok for sequental code, but sux if there is a lot of irq handling. /Pero

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