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We are attempting to interface to an audio grade 24-bit ADC (CS5344).

We are using SPI0 on an LPC2148 in slave mode, the ADC is the master.
We have verified that the incoming SPI data stream is valid with a
logic analyzer, and being clocked in at 5 MHz. However, we never get a
transfer complete status indicating data is available. Register S0SPSR
always returns 0 (zero).

Here is the statement we are using to test for transfer complete:
while ((S0SPSR & 0x80) == 0) ; // wait for transfer complete

Here is how we are configuring the SPI port:
// FEDC BA98 7654 3210
// 00 reserved
// 0 variable word size
// 1 CPHA (0 for SSEL framing)
// 1 CPOL (change on falling, sample on rising)
// 0 Master
// 0 LSBF
// 0 SP int enable
// 0000 word size if .2 = 1 (0000 = 16)
// 0000 reserved
// 0 0 1 8
#define SPI_Config 0x0018

APBDIV = 1; // pclk = cclk (12MHz osc, 60MHz cclk)
S0SPCR = 0; // clear control reg prior to config
PINSEL0 = (PINSEL0 & 0xffff00ff) | 0x5500; // configure I/O pins
for SPI in slave mode
FIO0DIR &= 0xffffff0f;
FIO0DIR |= 0x20; // set MOSI0 as an input
S0SPCCR = 8; // set clock divisor, not used in slave mode
x = S0SPSR; // empty status register
x = S0SPDR; // empty data register
S0SPCR = SPI_Config; // configure spi as slave with 8-bit transfers

We must not be configuring this device incorrectly. What are we missing?

Any ideas, suggestions, even sarcasm would be welcomed at this point!
TIA

------------------------------------



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Dnia 07-10-2008, wto o godzinie 03:24 +0000, jdehalas napisał(a):
[...]
> We must not be configuring this device incorrectly. What are we
> missing?
>
> Any ideas, suggestions, even sarcasm would be welcomed at this point!
Desperado ;-)
How You manage SSEL input line?
--
Albert
------------------------------------



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--- In l...@yahoogroups.com, Albert Bartoszko wrote:
>
> Dnia 07-10-2008, wto o godzinie 03:24 +0000, jdehalas napisa=C5=82(a):
> [...]
> > We must not be configuring this device incorrectly. What are we
> > missing?
> >=20
> > Any ideas, suggestions, even sarcasm would be welcomed at this=20
point!
> Desperado ;-)
> How You manage SSEL input line?
>=20
>=20
> --=20
> Albert
>
Albert,
Right now we are using the L/R signal from the ADC, this signal=20
toggles every 32 bits as the left and right channel data are=20
outputed.=20

This goes into a GPIO port and is echoed out to the SSEL line...
I'm not sure we are using the SSEL correctly, can you explain the=20
correct ussage of the SSEL line especially from a timing=20
perspective?=20

Thanks!!!!!

Jay

------------------------------------



(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )

--- In l...@yahoogroups.com, Albert Bartoszko wrote:
>
> Dnia 07-10-2008, wto o godzinie 03:24 +0000, jdehalas napisa=C5=82(a):
> [...]
> > We must not be configuring this device incorrectly. What are we
> > missing?
> >=20
> > Any ideas, suggestions, even sarcasm would be welcomed at this point!
> Desperado ;-)
> How You manage SSEL input line?
>=20
>=20
> --=20
> Albert
>
This is tied to a GPIO and brought low during init of the SPI port.
------------------------------------



(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )

--- In l...@yahoogroups.com, "jdehalas" wrote:
>
> --- In l...@yahoogroups.com, Albert Bartoszko wrote:
> >
> > Dnia 07-10-2008, wto o godzinie 03:24 +0000, jdehalas napisa=C5=82(a):
> > [...]
> > > We must not be configuring this device incorrectly. What are we
> > > missing?
> > >=20
> > > Any ideas, suggestions, even sarcasm would be welcomed at this=20
> point!
> > Desperado ;-)
> > How You manage SSEL input line?
> >=20
> >=20
> > --=20
> > Albert
> >
> Albert,
> Right now we are using the L/R signal from the ADC, this signal=20
> toggles every 32 bits as the left and right channel data are=20
> outputed.=20
>=20
> This goes into a GPIO port and is echoed out to the SSEL line...
>=20
>=20
> I'm not sure we are using the SSEL correctly, can you explain the=20
> correct ussage of the SSEL line especially from a timing=20
> perspective?=20
>=20
> Thanks!!!!!
>=20
> Jay
>
That is incorrect. SSEL is tied to a GPIO pin because the ADC does not
provide an SSEL signal. SSEL is brought low during initialization of
the SPI0 port.

During SPI initialization I monitor the L/R signal and when it goes
low I bring SSEL low (using the GPIO output) to synchronize on a byte
boundry.

------------------------------------



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