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The Pin Control Block (PCB) allows assigning pins to peripherals. Some,
like P0.0, can be GPIO, TXD0, or PWM1. TXD0 can only be assigned to P0.0.
Others, like EINT3, can be assigned to P0.9, P0.20, or P0.30. Has anyone
ever tried assigning EINT3 to all three? The users manual does not mention
what might happen if you do.

I have no need to do this, I don't intend to do this, so please don't tell
me I shouldn't. This is just something I noticed as I was typing up some
documentation.

--jc
[Non-text portions of this message have been removed]
------------------------------------



(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )

--- In l...@yahoogroups.com, "J.C. Wren" wrote:
>
> The Pin Control Block (PCB) allows assigning pins to peripherals.
Some,
> like P0.0, can be GPIO, TXD0, or PWM1. TXD0 can only be assigned
to P0.0.
> Others, like EINT3, can be assigned to P0.9, P0.20, or P0.30. Has
anyone
> ever tried assigning EINT3 to all three? The users manual does not
mention
> what might happen if you do.
>
> I have no need to do this, I don't intend to do this, so please
don't tell
> me I shouldn't. This is just something I noticed as I was typing
up some
> documentation.
>
> --jc
> [Non-text portions of this message have been removed]
>

JC,

You can connect all three interrupt 'inputs' to three external
interrupt generating sources. However, they must all have the same
characteristics, i.e. that they are all open collector outputs to
ground, normally high, then interrupt on a falling edge. This is
because you can only setup EINT3 to trigger on a level or edge
condition (you could poll it but that would not be practical in most
cases).

In any event, you would then need a method of polling the external
devices to determine which on caused the interrupt. Not so bad if
they all come from SPI based devices or common bus based devices.

If you want to reduce the latency associated with the post-polling,
then use seperate interrupts for each device (when possible).

This is how ISA and PCI devices are generally configured in a PC.

Regards,
Simon.
------------------------------------



(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )

Interesting to know. I was wondering if the PCB was smart enough to only
actually assign the last pin configured to the device. Given the smarts of
some of the other peripherals, I wouldn't have automatically precluded it.
Your comment about the open collector triggers another thought. The pin
must pass through a buffer with an enable before being gated into the
peripheral it's being assigned to. If this is a logic level buffer, the
open collector-ness of the pin won't matter. If it's an analog buffer, then
it would. But for a logic level buffer, this could result in one buffer
driving a high and another driving a low. Unless those buffers are
open-collector internally, it seems damage is a possibility. This scenario
arises if someone inadvertently assigns EINT3 to two pins, with one being
high and the other low.

Time to go digging through the ARM site and see if they have any
implementation details on the PCB.

--jc

On Mon, Oct 13, 2008 at 11:07 AM, simonb65 wrote:

> --- In l...@yahoogroups.com , "J.C. Wren"
> wrote:
> >
> > The Pin Control Block (PCB) allows assigning pins to peripherals.
> Some,
> > like P0.0, can be GPIO, TXD0, or PWM1. TXD0 can only be assigned
> to P0.0.
> > Others, like EINT3, can be assigned to P0.9, P0.20, or P0.30. Has
> anyone
> > ever tried assigning EINT3 to all three? The users manual does not
> mention
> > what might happen if you do.
> >
> > I have no need to do this, I don't intend to do this, so please
> don't tell
> > me I shouldn't. This is just something I noticed as I was typing
> up some
> > documentation.
> >
> > --jc
> >
> >
> > [Non-text portions of this message have been removed]
> > JC,
>
> You can connect all three interrupt 'inputs' to three external
> interrupt generating sources. However, they must all have the same
> characteristics, i.e. that they are all open collector outputs to
> ground, normally high, then interrupt on a falling edge. This is
> because you can only setup EINT3 to trigger on a level or edge
> condition (you could poll it but that would not be practical in most
> cases).
>
> In any event, you would then need a method of polling the external
> devices to determine which on caused the interrupt. Not so bad if
> they all come from SPI based devices or common bus based devices.
>
> If you want to reduce the latency associated with the post-polling,
> then use seperate interrupts for each device (when possible).
>
> This is how ISA and PCI devices are generally configured in a PC.
>
> Regards,
> Simon.
>
>
>
[Non-text portions of this message have been removed]
------------------------------------



(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )

I have actually used this on one of our boards. I ran out of separate
interrupt pins that were still available (not taken up by other special
functions). I also recall the manual *did* go into this (check the foot
notes), and if you used more than one input it specified you must use
level, not edge, type interrupts and it implements a wired-or (or 'and'
since it's inverted logic...)

Cheers,
Bruce

-----Original Message-----
From: l...@yahoogroups.com [mailto:l...@yahoogroups.com] On Behalf
Of J.C. Wren
Sent: Tuesday, 14 October 2008 2:28 AM
To: l...@yahoogroups.com
Subject: Re: [lpc2000] Re: LPC2148 Pin Control Block Query

Interesting to know. I was wondering if the PCB was smart enough to
only
actually assign the last pin configured to the device. Given the smarts
of
some of the other peripherals, I wouldn't have automatically precluded
it.
Your comment about the open collector triggers another thought. The pin
must pass through a buffer with an enable before being gated into the
peripheral it's being assigned to. If this is a logic level buffer, the
open collector-ness of the pin won't matter. If it's an analog buffer,
then
it would. But for a logic level buffer, this could result in one buffer
driving a high and another driving a low. Unless those buffers are
open-collector internally, it seems damage is a possibility. This
scenario
arises if someone inadvertently assigns EINT3 to two pins, with one
being
high and the other low.

Time to go digging through the ARM site and see if they have any
implementation details on the PCB.

--jc

On Mon, Oct 13, 2008 at 11:07 AM, simonb65
wrote:

> --- In l...@yahoogroups.com , "J.C.
Wren"
> wrote:
> >
> > The Pin Control Block (PCB) allows assigning pins to peripherals.
> Some,
> > like P0.0, can be GPIO, TXD0, or PWM1. TXD0 can only be assigned
> to P0.0.
> > Others, like EINT3, can be assigned to P0.9, P0.20, or P0.30. Has
> anyone
> > ever tried assigning EINT3 to all three? The users manual does not
> mention
> > what might happen if you do.
> >
> > I have no need to do this, I don't intend to do this, so please
> don't tell
> > me I shouldn't. This is just something I noticed as I was typing
> up some
> > documentation.
> >
> > --jc
> >
> >
> > [Non-text portions of this message have been removed]
> > JC,
>
> You can connect all three interrupt 'inputs' to three external
> interrupt generating sources. However, they must all have the same
> characteristics, i.e. that they are all open collector outputs to
> ground, normally high, then interrupt on a falling edge. This is
> because you can only setup EINT3 to trigger on a level or edge
> condition (you could poll it but that would not be practical in most
> cases).
>
> In any event, you would then need a method of polling the external
> devices to determine which on caused the interrupt. Not so bad if
> they all come from SPI based devices or common bus based devices.
>
> If you want to reduce the latency associated with the post-polling,
> then use seperate interrupts for each device (when possible).
>
> This is how ISA and PCI devices are generally configured in a PC.
>
> Regards,
> Simon.
>
>
>
[Non-text portions of this message have been removed]
------------------------------------



(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )

On Mon, 13 Oct 2008 11:27:40 -0400 J.C. Wren wrote:

> Unless those buffers are open-collector internally, it seems damage is
> a possibility. This scenario arises if someone inadvertently assigns
> EINT3 to two pins, with one being high and the other low.
>
> Time to go digging through the ARM site and see if they have any
> implementation details on the PCB.

maybe ARM isn't the proper digging site, because the implementation of
the PCB peripheral is philips/NXP territory.

-c
------------------------------------



(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )