Colleagues,
I've written a small program in IAR EWARM to test SPI. It runs, but
SCLK and MOSI do not show up on the oscilloscope. Here's the code,
which actually makes SPI transactions:
while(1)
{
S0SPCCR = 32; // SCLK rate
S0SPCR =
0x00000000 | // MOSI valid on raising edge of SCLK
(CPOL=CPHA=0)
0x00000020 | // master (AD7390 DAC is the slave)
0x00000000 | // MSbit first
0x00000000 | // SPI interrupt inhibited
0x000C0004; // transmit 12 bits (BitEnable, BITS)
DAC_xLD_FSET = DAC_xLD_MASK; // drive LD# high
S0SPDR = 0x7FF; // write to the data register (this will start the
transmission and clear the SPIF bit)
while ( !(S0SPSR & 0x80) ); // poll SPIF bit for the end of
transaction
DAC_xLD_FCLR = DAC_xLD_MASK; // drive LD# low (data gets written
from serial shift register to DAC register)
}
Here's the initialization of my SPI peripheral:
void SPI_Init()
{
PCONP_bit.PCSPI = 1;
PINSEL3 = 0x0003CF00;
}
With a scope, I can see the LD# line toggle up and down, so this program
doesn't hang while polling for SPIF. Rang-out the wiring - it seems
to be correct. Nothing is shorted to Vcc or GND. Added a pullup and
enabled SSEL in PINSEL3, following this advice:
http://tech.groups.yahoo.com/group/lpc2000/message/4363
<../../../message/4363> . Checked that PINSEL doesn't get
overwritten. But still no clock.
Could anyone spot an error? What else can I check?
Thanks,
- Nick
[Non-text portions of this message have been removed]
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Well, it was a hardware problem. I have mixed-up SSP0 pins (34, 37, 38) and SPI pins
(60, 61, 62). This is my 1st design with LPC2000.
The LPC23XX user manual says that SSP can be an SPI master. Out of curiosity: why does
the chip have 2 SSPs, which can do all SPI functions, and a redundant dedicated SPI
peripheral ? Which one is preferable?
- Nick
--- In l...@yahoogroups.com, "kender_a"
wrote:
> Colleagues,
>
> I've written a small program in IAR EWARM to test SPI. It runs, but
> SCLK and MOSI do not show up on the oscilloscope. [...]
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