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Discussion group dedicated to the Philips LPC2000 family of ARM MCUs
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difference between pending and disabling an interrupt - Ali Aghaeifar - Sep 8 15:07:32 2012
Hi
In NVIC of Cortex M3 there is a register for "pending" of interrupts.
what is difference between pending and disabling an interrupt?
Thanks.
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )
In NVIC of Cortex M3 there is a register for "pending" of interrupts.
what is difference between pending and disabling an interrupt?
Thanks.
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )
Re: difference between pending and disabling an interrupt - Triffid Hunter - Sep 9 0:22:41 2012
On Sun, Sep 9, 2012 at 5:07 AM, Ali Aghaeifar wrote:
> In NVIC of Cortex M3 there is a register for "pending" of interrupts.
> what is difference between pending and disabling an interrupt?
pending means waiting to happen. In the context of interrupts, it
means that the interrupt flag is asserted but the interrupt handler
hasn't been started yet.
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )
> In NVIC of Cortex M3 there is a register for "pending" of interrupts.
> what is difference between pending and disabling an interrupt?
pending means waiting to happen. In the context of interrupts, it
means that the interrupt flag is asserted but the interrupt handler
hasn't been started yet.
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )
Re: difference between pending and disabling an interrupt - Ali Aghaeifar - Sep 9 2:43:35 2012
Thanks you Triffid
But as I know by disabling an arbitrary interrupt, flag set too (let's consider timer matching flag). isn't it?
--- In l..., Triffid Hunter wrote:
>
> On Sun, Sep 9, 2012 at 5:07 AM, Ali Aghaeifar wrote:
> > In NVIC of Cortex M3 there is a register for "pending" of interrupts.
> > what is difference between pending and disabling an interrupt?
>
> pending means waiting to happen. In the context of interrupts, it
> means that the interrupt flag is asserted but the interrupt handler
> hasn't been started yet.
>
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )
But as I know by disabling an arbitrary interrupt, flag set too (let's consider timer matching flag). isn't it?
--- In l..., Triffid Hunter wrote:
>
> On Sun, Sep 9, 2012 at 5:07 AM, Ali Aghaeifar wrote:
> > In NVIC of Cortex M3 there is a register for "pending" of interrupts.
> > what is difference between pending and disabling an interrupt?
>
> pending means waiting to happen. In the context of interrupts, it
> means that the interrupt flag is asserted but the interrupt handler
> hasn't been started yet.
>
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )
Re: difference between pending and disabling an interrupt - Phil Young - Sep 9 3:07:30 2012
Pending means it is ready to trigger an ISR. The CPU can only so one thing
at a time, so if multiple interrupts are triggered the are pending until
they are serviced.
When reading the register it tells you which interrupts are pending, when
writing to it means setting an interrupt to the pending state.
When an interrupt is pending it is ready to trigger ( unless it is also
disabled in which case it will never trigger an interrupt) but it may simply
be that the exception priority that the CPU is running at is lower than the
priority of the pending interrupt.
In this case the interrupt is "pending", it will not occur until the
exception priority of the core rises to the appropriate level.
So for example you could execute an NMI during which you decide to trigger
an interrupt, then complete the NMI service routine and return to the main
program ( or exception handler that was pre-empted by the NMI ).
When you return from the NMI service routine the exception priority is
restored to the level of the routine that was executing, and if this is
higher than the level of the "pending" interrupt then the interrupt will
occur.
e.g.
Main
....
TimerISR
....
NMI
....
NMI pends interrupt for XXX
....
NMI returns
.... XXX remains in pending state
Timer ISR returns
XXX interrupt occurs
....
XXX interrupt returns
... back to main code
So disabling an interrupt means preventing it from occurring even if it is
triggered.
Pending it means scheduling it to occur as soon as possible.
Regards
Phil.
From: l... [mailto:l...] On Behalf Of
Ali Aghaeifar
Sent: 09 September 2012 07:43
To: l...
Subject: [lpc2000] Re: difference between pending and disabling an interrupt
Thanks you Triffid
But as I know by disabling an arbitrary interrupt, flag set too (let's
consider timer matching flag). isn't it?
--- In l... , Triffid
Hunter wrote:
>
> On Sun, Sep 9, 2012 at 5:07 AM, Ali Aghaeifar wrote:
> > In NVIC of Cortex M3 there is a register for "pending" of interrupts.
> > what is difference between pending and disabling an interrupt?
>
> pending means waiting to happen. In the context of interrupts, it
> means that the interrupt flag is asserted but the interrupt handler
> hasn't been started yet.
>
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )
at a time, so if multiple interrupts are triggered the are pending until
they are serviced.
When reading the register it tells you which interrupts are pending, when
writing to it means setting an interrupt to the pending state.
When an interrupt is pending it is ready to trigger ( unless it is also
disabled in which case it will never trigger an interrupt) but it may simply
be that the exception priority that the CPU is running at is lower than the
priority of the pending interrupt.
In this case the interrupt is "pending", it will not occur until the
exception priority of the core rises to the appropriate level.
So for example you could execute an NMI during which you decide to trigger
an interrupt, then complete the NMI service routine and return to the main
program ( or exception handler that was pre-empted by the NMI ).
When you return from the NMI service routine the exception priority is
restored to the level of the routine that was executing, and if this is
higher than the level of the "pending" interrupt then the interrupt will
occur.
e.g.
Main
....
TimerISR
....
NMI
....
NMI pends interrupt for XXX
....
NMI returns
.... XXX remains in pending state
Timer ISR returns
XXX interrupt occurs
....
XXX interrupt returns
... back to main code
So disabling an interrupt means preventing it from occurring even if it is
triggered.
Pending it means scheduling it to occur as soon as possible.
Regards
Phil.
From: l... [mailto:l...] On Behalf Of
Ali Aghaeifar
Sent: 09 September 2012 07:43
To: l...
Subject: [lpc2000] Re: difference between pending and disabling an interrupt
Thanks you Triffid
But as I know by disabling an arbitrary interrupt, flag set too (let's
consider timer matching flag). isn't it?
--- In l... , Triffid
Hunter wrote:
>
> On Sun, Sep 9, 2012 at 5:07 AM, Ali Aghaeifar wrote:
> > In NVIC of Cortex M3 there is a register for "pending" of interrupts.
> > what is difference between pending and disabling an interrupt?
>
> pending means waiting to happen. In the context of interrupts, it
> means that the interrupt flag is asserted but the interrupt handler
> hasn't been started yet.
>
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )
Re: difference between pending and disabling an interrupt - FreeRTOS Info - Sep 9 3:10:08 2012
> But as I know by disabling an arbitrary interrupt, flag set too (let's
> consider timer matching flag). isn't it?
I don't understand you last point here - sorry.
I sent the following reply last night, but from the wrong email address,
so it bounced.:
> In NVIC of Cortex M3 there is a register for "pending" of interrupts.
> what is difference between pending and disabling an interrupt?
If you disable an interrupt, it will never execute (it is disabled).
For an interrupt to execute both it and the global interrupt flag must
both be enabled.
Pending an interrupt will trigger an interrupt, just as if the interrupt
was triggered by a peripheral or an external interrupt line. Once an
interrupt is pending it will execute as soon as the interrupt is
enabled, and it is the highest priority interrupt that is pending.
Regards,
Richard.
+ http://www.FreeRTOS.org
Designed for microcontrollers. More than 7000 downloads per month.
+ http://www.FreeRTOS.org/trace
15 interconnected trace views. An indispensable productivity tool.
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )
Re: difference between pending and disabling an interrupt - Ali Aghaeifar - Sep 9 4:00:45 2012
Thank you Richard,
Your answer was completely satisfies me.
--- In l..., FreeRTOS Info wrote:
> > But as I know by disabling an arbitrary interrupt, flag set too (let's
> > consider timer matching flag). isn't it?
> I don't understand you last point here - sorry.
>
> I sent the following reply last night, but from the wrong email address,
> so it bounced.:
>
> > In NVIC of Cortex M3 there is a register for "pending" of interrupts.
> > what is difference between pending and disabling an interrupt?
>
> If you disable an interrupt, it will never execute (it is disabled).
> For an interrupt to execute both it and the global interrupt flag must
> both be enabled.
>
> Pending an interrupt will trigger an interrupt, just as if the interrupt
> was triggered by a peripheral or an external interrupt line. Once an
> interrupt is pending it will execute as soon as the interrupt is
> enabled, and it is the highest priority interrupt that is pending.
> Regards,
> Richard.
>
> + http://www.FreeRTOS.org
> Designed for microcontrollers. More than 7000 downloads per month.
>
> + http://www.FreeRTOS.org/trace
> 15 interconnected trace views. An indispensable productivity tool.
>
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )
Your answer was completely satisfies me.
--- In l..., FreeRTOS Info wrote:
> > But as I know by disabling an arbitrary interrupt, flag set too (let's
> > consider timer matching flag). isn't it?
> I don't understand you last point here - sorry.
>
> I sent the following reply last night, but from the wrong email address,
> so it bounced.:
>
> > In NVIC of Cortex M3 there is a register for "pending" of interrupts.
> > what is difference between pending and disabling an interrupt?
>
> If you disable an interrupt, it will never execute (it is disabled).
> For an interrupt to execute both it and the global interrupt flag must
> both be enabled.
>
> Pending an interrupt will trigger an interrupt, just as if the interrupt
> was triggered by a peripheral or an external interrupt line. Once an
> interrupt is pending it will execute as soon as the interrupt is
> enabled, and it is the highest priority interrupt that is pending.
> Regards,
> Richard.
>
> + http://www.FreeRTOS.org
> Designed for microcontrollers. More than 7000 downloads per month.
>
> + http://www.FreeRTOS.org/trace
> 15 interconnected trace views. An indispensable productivity tool.
>
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )
Re: difference between pending and disabling an interrupt - Ali Aghaeifar - Sep 9 4:03:07 2012
Thank you Phil for your perfect answer.
--- In l..., "Phil Young" wrote:
>
> Pending means it is ready to trigger an ISR. The CPU can only so one thing
> at a time, so if multiple interrupts are triggered the are pending until
> they are serviced.
>
> When reading the register it tells you which interrupts are pending, when
> writing to it means setting an interrupt to the pending state.
>
> When an interrupt is pending it is ready to trigger ( unless it is also
> disabled in which case it will never trigger an interrupt) but it may simply
> be that the exception priority that the CPU is running at is lower than the
> priority of the pending interrupt.
>
>
>
> In this case the interrupt is "pending", it will not occur until the
> exception priority of the core rises to the appropriate level.
>
>
>
> So for example you could execute an NMI during which you decide to trigger
> an interrupt, then complete the NMI service routine and return to the main
> program ( or exception handler that was pre-empted by the NMI ).
>
> When you return from the NMI service routine the exception priority is
> restored to the level of the routine that was executing, and if this is
> higher than the level of the "pending" interrupt then the interrupt will
> occur.
>
>
>
> e.g.
>
>
>
>
>
> Main
>
> ....
>
> TimerISR
>
> ....
>
> NMI
>
> ....
>
> NMI pends interrupt for XXX
>
> ....
>
> NMI returns
>
> .... XXX remains in pending state
>
> Timer ISR returns
>
> XXX interrupt occurs
>
> ....
>
> XXX interrupt returns
>
> ... back to main code
>
>
>
>
>
> So disabling an interrupt means preventing it from occurring even if it is
> triggered.
>
> Pending it means scheduling it to occur as soon as possible.
>
> Regards
>
>
>
> Phil.
>
>
>
> From: l... [mailto:l...] On Behalf Of
> Ali Aghaeifar
> Sent: 09 September 2012 07:43
> To: l...
> Subject: [lpc2000] Re: difference between pending and disabling an interrupt
>
>
>
>
>
> Thanks you Triffid
>
> But as I know by disabling an arbitrary interrupt, flag set too (let's
> consider timer matching flag). isn't it?
>
> --- In l... , Triffid
> Hunter wrote:
> >
> > On Sun, Sep 9, 2012 at 5:07 AM, Ali Aghaeifar wrote:
> > > In NVIC of Cortex M3 there is a register for "pending" of interrupts.
> > > what is difference between pending and disabling an interrupt?
> >
> > pending means waiting to happen. In the context of interrupts, it
> > means that the interrupt flag is asserted but the interrupt handler
> > hasn't been started yet.
> >
>
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )
--- In l..., "Phil Young" wrote:
>
> Pending means it is ready to trigger an ISR. The CPU can only so one thing
> at a time, so if multiple interrupts are triggered the are pending until
> they are serviced.
>
> When reading the register it tells you which interrupts are pending, when
> writing to it means setting an interrupt to the pending state.
>
> When an interrupt is pending it is ready to trigger ( unless it is also
> disabled in which case it will never trigger an interrupt) but it may simply
> be that the exception priority that the CPU is running at is lower than the
> priority of the pending interrupt.
>
>
>
> In this case the interrupt is "pending", it will not occur until the
> exception priority of the core rises to the appropriate level.
>
>
>
> So for example you could execute an NMI during which you decide to trigger
> an interrupt, then complete the NMI service routine and return to the main
> program ( or exception handler that was pre-empted by the NMI ).
>
> When you return from the NMI service routine the exception priority is
> restored to the level of the routine that was executing, and if this is
> higher than the level of the "pending" interrupt then the interrupt will
> occur.
>
>
>
> e.g.
>
>
>
>
>
> Main
>
> ....
>
> TimerISR
>
> ....
>
> NMI
>
> ....
>
> NMI pends interrupt for XXX
>
> ....
>
> NMI returns
>
> .... XXX remains in pending state
>
> Timer ISR returns
>
> XXX interrupt occurs
>
> ....
>
> XXX interrupt returns
>
> ... back to main code
>
>
>
>
>
> So disabling an interrupt means preventing it from occurring even if it is
> triggered.
>
> Pending it means scheduling it to occur as soon as possible.
>
> Regards
>
>
>
> Phil.
>
>
>
> From: l... [mailto:l...] On Behalf Of
> Ali Aghaeifar
> Sent: 09 September 2012 07:43
> To: l...
> Subject: [lpc2000] Re: difference between pending and disabling an interrupt
>
>
>
>
>
> Thanks you Triffid
>
> But as I know by disabling an arbitrary interrupt, flag set too (let's
> consider timer matching flag). isn't it?
>
> --- In l... , Triffid
> Hunter wrote:
> >
> > On Sun, Sep 9, 2012 at 5:07 AM, Ali Aghaeifar wrote:
> > > In NVIC of Cortex M3 there is a register for "pending" of interrupts.
> > > what is difference between pending and disabling an interrupt?
> >
> > pending means waiting to happen. In the context of interrupts, it
> > means that the interrupt flag is asserted but the interrupt handler
> > hasn't been started yet.
> >
>
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )