Hi Group,
I'm trying to setup the EMC Config for LPC1788 with 2 MT48LC16M16.
One Memory Chip is connected with D0 ... D15 the other one with
D16 .. D31, so that both give me 32 Bit Data Bus.
My IO Config look like following:
//--------------------------------// Pin Config
// P3.00 ... P3.31: 'D' EMC.D00 ... EMC.D31
IOCON_P3_00 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_01 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_02 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_03 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_04 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_05 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_06 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_07 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_08 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_09 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_10 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_11 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_12 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_13 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_14 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_15 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_16 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_17 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_18 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_19 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_20 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_21 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_22 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_23 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_24 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_25 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_26 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_27 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_28 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_29 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_30 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P3_31 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
// P4.00 .. P4.21: 'D' EMC.A00 ... EMC.A21
IOCON_P4_00 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P4_01 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P4_02 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P4_03 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P4_04 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P4_05 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P4_06 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P4_07 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P4_08 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P4_09 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P4_10 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P4_11 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P4_12 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P4_13 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P4_14 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P4_15 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P4_16 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
IOCON_P4_17 = IOCON(1, IO_MODE_NONE, IO_HYS_ENABLE, 0, 0, 0, 0);
// P4.04 .. P4.21: 'D' Memory Control
IOCON_P4_24 = 1; // RD
IOCON_P4_25 = 1; // WR
IOCON_P2_16 = 1; // CAS
IOCON_P2_17 = 1; // RAS
IOCON_P2_20 = 1; // Dyn.CS0
IOCON_P2_18 = 1; // Clk.0
IOCON_P2_24 = 1; // Cke.0
IOCON_P2_28 = 1; // DQMO.0
IOCON_P2_29 = 1; // DQMO.1
IOCON_P2_30 = 1; // DQMO.2
IOCON_P2_31 = 1; // DQMO.3
PCONP_bit.PCEMC = 1; // External Memory Controller Power 'On'
EMCControl = 1; // External Memory Controller Enable
EMCConfig = 0; // Default Config
//--------------------------------// Dynamic RAM Config
Int32U iDelayConstant = 0x00000A05; // Für 60MHz DRAM
//---- !!!! Reset Config
EMCDLYCTL = iDelayConstant; //DRAM Delay
EMCDynamicConfig0 = 0x00005400; //13 row, 9 - col, SDRAM
EMCDynamicReadConfig = 1; //Command delayed strategy
EMCDynamictRP = 2; //
EMCDynamictRAS = 3; //
EMCDynamictSREX = 10; //
EMCDynamictAPR = 2; //
EMCDynamictDAL = 5; //
EMCDynamictWR = 2; //
EMCDynamictRC = 6; //
EMCDynamictRFC = 6; //
EMCDynamictXSR = 8; //
EMCDynamictRRD = 3; //
EMCDynamictMRD = 3; //
// JEDEC General SDRAM Initialization Sequence
// DELAY to allow power and clocks to stabilize ~200 ms NOP
EMCDynamicControl = 0x0183;
Delay_uS(300000);
// PRECHARGE-ALL, shortest possible refresh period
EMCDynamicControl = 0x0103;
EMCDynamicRefresh = 1;
Delay_uS(2000);
// Set Normal Refresh
EMCDynamicRefresh = 0x28;
Delay_uS(1000);
// COMM
EMCDynamicControl = 0x0083;
volatile unsigned long Dummy;
Dummy = *((volatile unsigned int*)(MEM_DRAM1_BASE + (0x33UL << 12)));
Delay_uS(100);
// NORM
EMCDynamicControl = 0x00000000;
EMCDynamicConfig0 |= 0x00080000; // Enable buffer
Delay_uS(100000);
My Problem is, that these Configs seems to work.
I can read/write to differnt Adresses, but some Adresses (Data)
get corrupt. Funny is, that, when i look to such adresses in
Debug Mode, every thing looks fine, ..
I'm pretty sure, that i have done some mistake, does anyone has
an idea??
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