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Discussion Groups | LPC2000 | 2106 as a SPI slave
Discussion group dedicated to the Philips LPC2000 family of ARM MCUs
2106 as a SPI slave - jay_pni - Jul 15 17:11:00 2005
We are using the 2106 as a SPI slave device with CPOL = 0, CPHA = 0, MSB. We are able
to
always receive commands OK, but are having problems sending commands back. If the
master provides the SCLK at too SLOW of a rate, the data from the 2106 is shifted to the left
by 1 after the fist byte sent back. Having the master speed up the SCLK takes care of this
problem and data sent from the 2106 on the MISO line is fine, however smaller processors
are unable to provide a fast enough clock rate (bit banging). Other than the SPI registers, are
there any other registers (powering off other peripherals not being used) that should be set?
Thanks
Jay
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )
always receive commands OK, but are having problems sending commands back. If the
master provides the SCLK at too SLOW of a rate, the data from the 2106 is shifted to the left
by 1 after the fist byte sent back. Having the master speed up the SCLK takes care of this
problem and data sent from the 2106 on the MISO line is fine, however smaller processors
are unable to provide a fast enough clock rate (bit banging). Other than the SPI registers, are
there any other registers (powering off other peripherals not being used) that should be set?
Thanks
Jay
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )
Re: 2106 as a SPI slave - Mark Butcher - Jul 19 19:50:00 2005
Hi Jay
It is interesting what you write. I intended using the LPC2106 in
slave SPI mode a few months ago when interfacing it it to a
Freescale NE64 as 100M LAN coprocessor. The data was always received
by the LPC correctly but what it sent back was irregular. I
eventually gave up and use it in Master mode concluding that the SPI
has errors. In master mode there are no problems.
If you search the archives you should find my original message which
give much more details.
I have an embedded web server running at http://212.254.22.36/ for
test purposes if you are interested.
Cheers
Mark Butcher
www.mjbc.ch
--- In lpc2000@lpc2..., "jay_pni" <jay_pni@y...> wrote:
> We are using the 2106 as a SPI slave device with CPOL = 0, CPHA =
0, MSB. We are able to
> always receive commands OK, but are having problems sending
commands back. If the
> master provides the SCLK at too SLOW of a rate, the data from the
2106 is shifted to the left
> by 1 after the fist byte sent back. Having the master speed up
the SCLK takes care of this
> problem and data sent from the 2106 on the MISO line is fine,
however smaller processors
> are unable to provide a fast enough clock rate (bit banging).
Other than the SPI registers, are
> there any other registers (powering off other peripherals not
being used) that should be set?
>
> Thanks
>
> Jay
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )
It is interesting what you write. I intended using the LPC2106 in
slave SPI mode a few months ago when interfacing it it to a
Freescale NE64 as 100M LAN coprocessor. The data was always received
by the LPC correctly but what it sent back was irregular. I
eventually gave up and use it in Master mode concluding that the SPI
has errors. In master mode there are no problems.
If you search the archives you should find my original message which
give much more details.
I have an embedded web server running at http://212.254.22.36/ for
test purposes if you are interested.
Cheers
Mark Butcher
www.mjbc.ch
--- In lpc2000@lpc2..., "jay_pni" <jay_pni@y...> wrote:
> We are using the 2106 as a SPI slave device with CPOL = 0, CPHA =
0, MSB. We are able to
> always receive commands OK, but are having problems sending
commands back. If the
> master provides the SCLK at too SLOW of a rate, the data from the
2106 is shifted to the left
> by 1 after the fist byte sent back. Having the master speed up
the SCLK takes care of this
> problem and data sent from the 2106 on the MISO line is fine,
however smaller processors
> are unable to provide a fast enough clock rate (bit banging).
Other than the SPI registers, are
> there any other registers (powering off other peripherals not
being used) that should be set?
>
> Thanks
>
> Jay
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )