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Discussion Groups | MSP430 | MSP430F5435 BSL Connections
The purpose of this group is to foster exchange of information on the Texas Instruments MSP430 family of microcontrollers and related tools. Everyone welcome, all levels of familiarity/expertise.
MSP430F5435 BSL Connections - johnh_bassett - Oct 16 10:52:48 2009
Having problems getting BSL to work on F5435. Everything else works, including JTAG.
I'm using BSL_Scripter.exe and custom level-shifting hardware.
I can see reset and RTS signals on scope and can send first command (TX_BSL_VERSION), but get nothing returned, not even an acknowledge.
DTR (reset) and RTS are double-inverted from RS232 polarity.
I have the RTS signal going to TCK pin 75.
I'm worried about the RTS signal and whether it should connect to TCK (pin 75) or TEST (pin 71) on processor.
SLAU265 section 2.2.2 says that processors with more than 28 pins and have dedicated JTAG should use the TCK signal.
The Errata sheet for MSP430F5435 section JTAG20 talks about using the TEST signal for BSL.
Has anyone tried this? I haven't found a reference design for the F5435 that shows BSL.
If TCK is the correct, should I pull TEST high or low when not used by JTAG?
Thanks
John
------------------------------------
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I'm using BSL_Scripter.exe and custom level-shifting hardware.
I can see reset and RTS signals on scope and can send first command (TX_BSL_VERSION), but get nothing returned, not even an acknowledge.
DTR (reset) and RTS are double-inverted from RS232 polarity.
I have the RTS signal going to TCK pin 75.
I'm worried about the RTS signal and whether it should connect to TCK (pin 75) or TEST (pin 71) on processor.
SLAU265 section 2.2.2 says that processors with more than 28 pins and have dedicated JTAG should use the TCK signal.
The Errata sheet for MSP430F5435 section JTAG20 talks about using the TEST signal for BSL.
Has anyone tried this? I haven't found a reference design for the F5435 that shows BSL.
If TCK is the correct, should I pull TEST high or low when not used by JTAG?
Thanks
John
------------------------------------
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
Re: MSP430F5435 BSL Connections - old_cow_yellow - Oct 16 16:49:12 2009
There is a reference design for PC com-port to BSL. It can be found in Chap=
ter 5 and 7 in slau265.
DTR from PC should go through a non-inverting level translator and then go =
to nRST pin. That is, when DTR is +12V (nominal), nRST should be +3V (nomin=
al). When DTR is =9612V (nominal), nRST should be 0V.
RTS from PC should go through an inverting level translator and then go to =
TEST pin. That is, when RTS is +12V (nominal), TEST should be 0V. When RTS =
is =9612V (nominal), TEST should be 3V (nominal).
OCY
--- In m...@yahoogroups.com, "johnh_bassett" wrote:
>
> Having problems getting BSL to work on F5435. Everything else works, incl=
uding JTAG.
>=20
> I'm using BSL_Scripter.exe and custom level-shifting hardware.
>=20
> I can see reset and RTS signals on scope and can send first command (TX_B=
SL_VERSION), but get nothing returned, not even an acknowledge.
>=20
> DTR (reset) and RTS are double-inverted from RS232 polarity.
>=20
> I have the RTS signal going to TCK pin 75.
>=20
> I'm worried about the RTS signal and whether it should connect to TCK (pi=
n 75) or TEST (pin 71) on processor.
>=20
> SLAU265 section 2.2.2 says that processors with more than 28 pins and hav=
e dedicated JTAG should use the TCK signal.
>=20
> The Errata sheet for MSP430F5435 section JTAG20 talks about using the TES=
T signal for BSL.
>=20
> Has anyone tried this? I haven't found a reference design for the F5435 t=
hat shows BSL.
>=20
> If TCK is the correct, should I pull TEST high or low when not used by JT=
AG?
>=20
> Thanks
>=20
> John
>
------------------------------------
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
ter 5 and 7 in slau265.
DTR from PC should go through a non-inverting level translator and then go =
to nRST pin. That is, when DTR is +12V (nominal), nRST should be +3V (nomin=
al). When DTR is =9612V (nominal), nRST should be 0V.
RTS from PC should go through an inverting level translator and then go to =
TEST pin. That is, when RTS is +12V (nominal), TEST should be 0V. When RTS =
is =9612V (nominal), TEST should be 3V (nominal).
OCY
--- In m...@yahoogroups.com, "johnh_bassett"
>
> Having problems getting BSL to work on F5435. Everything else works, incl=
uding JTAG.
>=20
> I'm using BSL_Scripter.exe and custom level-shifting hardware.
>=20
> I can see reset and RTS signals on scope and can send first command (TX_B=
SL_VERSION), but get nothing returned, not even an acknowledge.
>=20
> DTR (reset) and RTS are double-inverted from RS232 polarity.
>=20
> I have the RTS signal going to TCK pin 75.
>=20
> I'm worried about the RTS signal and whether it should connect to TCK (pi=
n 75) or TEST (pin 71) on processor.
>=20
> SLAU265 section 2.2.2 says that processors with more than 28 pins and hav=
e dedicated JTAG should use the TCK signal.
>=20
> The Errata sheet for MSP430F5435 section JTAG20 talks about using the TES=
T signal for BSL.
>=20
> Has anyone tried this? I haven't found a reference design for the F5435 t=
hat shows BSL.
>=20
> If TCK is the correct, should I pull TEST high or low when not used by JT=
AG?
>=20
> Thanks
>=20
> John
>
------------------------------------
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
Re: MSP430F5435 BSL Connections - johnh_bassett - Oct 20 4:43:01 2009
Thanks OCY,
I am now running BSL on the 'F5435, using the TEST pin.
For general information: the BSL_Scripter program needs to use the INIT_COM=
M 5438 mode, not FLASH mode, for MSP430F5435. It should have been obvious, =
but it took me a while to work it out!
John
--- In m...@yahoogroups.com, "old_cow_yellow" wrote:
>
> There is a reference design for PC com-port to BSL. It can be found in Ch=
apter 5 and 7 in slau265.
>=20
> DTR from PC should go through a non-inverting level translator and then g=
o to nRST pin. That is, when DTR is +12V (nominal), nRST should be +3V (nom=
inal). When DTR is =9612V (nominal), nRST should be 0V.
>=20
> RTS from PC should go through an inverting level translator and then go t=
o TEST pin. That is, when RTS is +12V (nominal), TEST should be 0V. When RT=
S is =9612V (nominal), TEST should be 3V (nominal).
>=20
> OCY
>=20
> --- In m...@yahoogroups.com, "johnh_bassett" wrote:
> >
> > Having problems getting BSL to work on F5435. Everything else works, in=
cluding JTAG.
> >=20
> > I'm using BSL_Scripter.exe and custom level-shifting hardware.
> >=20
> > I can see reset and RTS signals on scope and can send first command (TX=
_BSL_VERSION), but get nothing returned, not even an acknowledge.
> >=20
> > DTR (reset) and RTS are double-inverted from RS232 polarity.
> >=20
> > I have the RTS signal going to TCK pin 75.
> >=20
> > I'm worried about the RTS signal and whether it should connect to TCK (=
pin 75) or TEST (pin 71) on processor.
> >=20
> > SLAU265 section 2.2.2 says that processors with more than 28 pins and h=
ave dedicated JTAG should use the TCK signal.
> >=20
> > The Errata sheet for MSP430F5435 section JTAG20 talks about using the T=
EST signal for BSL.
> >=20
> > Has anyone tried this? I haven't found a reference design for the F5435=
that shows BSL.
> >=20
> > If TCK is the correct, should I pull TEST high or low when not used by =
JTAG?
> >=20
> > Thanks
> >=20
> > John
>
------------------------------------
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
I am now running BSL on the 'F5435, using the TEST pin.
For general information: the BSL_Scripter program needs to use the INIT_COM=
M 5438 mode, not FLASH mode, for MSP430F5435. It should have been obvious, =
but it took me a while to work it out!
John
--- In m...@yahoogroups.com, "old_cow_yellow"
>
> There is a reference design for PC com-port to BSL. It can be found in Ch=
apter 5 and 7 in slau265.
>=20
> DTR from PC should go through a non-inverting level translator and then g=
o to nRST pin. That is, when DTR is +12V (nominal), nRST should be +3V (nom=
inal). When DTR is =9612V (nominal), nRST should be 0V.
>=20
> RTS from PC should go through an inverting level translator and then go t=
o TEST pin. That is, when RTS is +12V (nominal), TEST should be 0V. When RT=
S is =9612V (nominal), TEST should be 3V (nominal).
>=20
> OCY
>=20
> --- In m...@yahoogroups.com, "johnh_bassett"
> >
> > Having problems getting BSL to work on F5435. Everything else works, in=
cluding JTAG.
> >=20
> > I'm using BSL_Scripter.exe and custom level-shifting hardware.
> >=20
> > I can see reset and RTS signals on scope and can send first command (TX=
_BSL_VERSION), but get nothing returned, not even an acknowledge.
> >=20
> > DTR (reset) and RTS are double-inverted from RS232 polarity.
> >=20
> > I have the RTS signal going to TCK pin 75.
> >=20
> > I'm worried about the RTS signal and whether it should connect to TCK (=
pin 75) or TEST (pin 71) on processor.
> >=20
> > SLAU265 section 2.2.2 says that processors with more than 28 pins and h=
ave dedicated JTAG should use the TCK signal.
> >=20
> > The Errata sheet for MSP430F5435 section JTAG20 talks about using the T=
EST signal for BSL.
> >=20
> > Has anyone tried this? I haven't found a reference design for the F5435=
that shows BSL.
> >=20
> > If TCK is the correct, should I pull TEST high or low when not used by =
JTAG?
> >=20
> > Thanks
> >=20
> > John
>
------------------------------------
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )