Guys
This might sound silly but I am trying to generate 25.7KHz frequency signal from MSP430. The signal should be like this.

25.7KHz pulses for 2ms duration then stay off for another 2ms duration. This keeps on repeating.

I would need some suggestions on how to generate this kind of signal. I have tried many things but failed.

THanks!

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[Non-text portions of this message have been removed]

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I think that using a pwm output, and by software programming an ON / OFF
modulation each 2 ms.
Other way could be by hardware using the dma.

Vishal Kema escribió:
>
>
> Guys
> This might sound silly but I am trying to generate 25.7KHz frequency
> signal from MSP430. The signal should be like this.
>
> 25.7KHz pulses for 2ms duration then stay off for another 2ms
> duration. This keeps on repeating.
>
> I would need some suggestions on how to generate this kind of signal.
> I have tried many things but failed.
>
> THanks!
>
> >From cricket scores to your friends. Try the Yahoo! India Homepage!
> http://in.yahoo.com/trynew [Non-text portions of this message have been removed]

------------------------------------

______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.


(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )

First a question: How exact must the timing be? 1/25.7kHz is not an integer ms value (there are 51.4 pulses in 2ms).

One easy way to do it would be to generate 2 signals: the 25.7kHz and the 2ms. You can the just put them through an AND or OR gate (depending on the value you need for the idle state) and you get your OOK signal. But there will be a very short pulse at the beginning and at the end of each frequency pulse.

Another way is quite similar, but you use a mod 51 prescaller and use its output for the AND gate. You can even use the other timer to do the prescaller (input to the timer the output frequency of 25.7kHz)

Regards,
Michael K.

--- In m...@yahoogroups.com, Vishal Kema wrote:
>
> Guys
> This might sound silly but I am trying to generate 25.7KHz frequency signal from MSP430. The signal should be like this.
>
> 25.7KHz pulses for 2ms duration then stay off for another 2ms duration. This keeps on repeating.
>
> I would need some suggestions on how to generate this kind of signal. I have tried many things but failed.
>
> THanks!
>
> From cricket scores to your friends. Try the Yahoo! India Homepage! http://in.yahoo.com/trynew
>
> [Non-text portions of this message have been removed]
>

------------------------------------



(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )

Choose a MSP with DMA, then use Repeated Single Transfer mode to
transfer a look-up table of time constants to the timer B reload
register, one cycle at a time. The table should contain an even
number of high-frequency entries for the 25.7kHz portion of the
output (102) and a single low-frequency entry (bigger number) for the
'off' portion of the output. Each roll-over of timer B - use CCR0 -
triggers a DMA transfer of the new timer-reload value to timer B.
This way you transfer 102 identical short time periods after each of
which the timer output toggles (giving you a burst of 2mSecs of 51
frequency cycles on the output) and then transfer 1 long time period
which gives you a 2mSec quiet period. Setting the DMA size count to
103 (ie 102 + 1) causes the sequence to automatically repeat with no
cpu intervention. Examine the timer output modes to decide what works
best for you, typically toggle or whatever, and remember to set the
initial condition to ensure the quiet period is low and not high.

Let's assume a 12MHz clock. A high frequency table entry of 232 in
the first 102 locations will give a toggle frequency (remember there
are 2 count cycles in toggle mode) of 12MHz/(2*(232+1)) or 25.751kHz
and a total elapsed time of 102*(232+1)/12MHz or 1.9805mSecs. Thus to
ensure the total cycle takes 4mSecs, the quiet period must be
2.0195mSec, or in other words the last table entry will be
12MHz/2.0195mSec or 24234.

Voila - no interrupts, no external hardware.

Hugh

At 06:15 AM 11/2/2009, you wrote:
>First a question: How exact must the timing be? 1/25.7kHz is not an
>integer ms value (there are 51.4 pulses in 2ms).
>
>One easy way to do it would be to generate 2 signals: the 25.7kHz
>and the 2ms. You can the just put them through an AND or OR gate
>(depending on the value you need for the idle state) and you get
>your OOK signal. But there will be a very short pulse at the
>beginning and at the end of each frequency pulse.
>
>Another way is quite similar, but you use a mod 51 prescaller and
>use its output for the AND gate. You can even use the other timer to
>do the prescaller (input to the timer the output frequency of 25.7kHz)
>
>Regards,
>Michael K.
>
>--- In m...@yahoogroups.com, Vishal Kema wrote:
> >
> > Guys
> > This might sound silly but I am trying to generate 25.7KHz
> frequency signal from MSP430. The signal should be like this.
> >
> > 25.7KHz pulses for 2ms duration then stay off for another 2ms
> duration. This keeps on repeating.
> >
> > I would need some suggestions on how to generate this kind of
> signal. I have tried many things but failed.
> >
> > THanks!
> >
> >
> >
> > From cricket scores to your friends. Try the Yahoo! India
> Homepage! http://in.yahoo.com/trynew
> >
> > [Non-text portions of this message have been removed]
> >
>------------------------------------



(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )

Typo, the last table entry will be 12MHz * 2.0195mSec = 24234, and
also use 24234-1 or 24233 as the last table entry.

Also a more robust design would use Toggle/Set rather than simply
Toggle; this way the output is set high whenever the count reaches
TBCL0 and is reset low whenever the count reaches TBCL1. Use Up mode
to repeatedly count up from 0 to the value in TBCL0 with the output
toggle low occurring when the count reaches TBCL1. TBCL1 always holds
the fixed value of 233 and TBCL0 is loaded by the DMA from the table
as described in my earlier post, 102 times with 232 and once with
24233. Note TBCL0 load mode must not be Immediate, since otherwise
the count on the last table entry of 232 would not reset to 0 because
the DMA would have already populated the new (higher) count value;
use instead mode 01 where the new value is loaded when the count has
safely reset to 0. Ensure that the TBCCR0 interrupt enable flag CCIE
is not set, by the way; if it is then DMA transfers are blocked as
you can't use interrupts at the same time as DMA on TBCCR0. If
interrupts are a requirement for some reason, use instead TBCCR2.

If 25.71kHz is not accurate enough you can select the crystal
frequency for a better match or use the FLL where available to tune
the frequency.

Hugh

At 08:30 AM 11/2/2009, you wrote:
>Choose a MSP with DMA, then use Repeated Single Transfer mode to
>transfer a look-up table of time constants to the timer B reload
>register, one cycle at a time. The table should contain an even
>number of high-frequency entries for the 25.7kHz portion of the
>output (102) and a single low-frequency entry (bigger number) for the
>'off' portion of the output. Each roll-over of timer B - use CCR0 -
>triggers a DMA transfer of the new timer-reload value to timer B.
>This way you transfer 102 identical short time periods after each of
>which the timer output toggles (giving you a burst of 2mSecs of 51
>frequency cycles on the output) and then transfer 1 long time period
>which gives you a 2mSec quiet period. Setting the DMA size count to
>103 (ie 102 + 1) causes the sequence to automatically repeat with no
>cpu intervention. Examine the timer output modes to decide what works
>best for you, typically toggle or whatever, and remember to set the
>initial condition to ensure the quiet period is low and not high.
>
>Let's assume a 12MHz clock. A high frequency table entry of 232 in
>the first 102 locations will give a toggle frequency (remember there
>are 2 count cycles in toggle mode) of 12MHz/(2*(232+1)) or 25.751kHz
>and a total elapsed time of 102*(232+1)/12MHz or 1.9805mSecs. Thus to
>ensure the total cycle takes 4mSecs, the quiet period must be
>2.0195mSec, or in other words the last table entry will be
>12MHz/2.0195mSec or 24234.
>
>Voila - no interrupts, no external hardware.
>
>Hugh
>
>At 06:15 AM 11/2/2009, you wrote:
> >First a question: How exact must the timing be? 1/25.7kHz is not an
> >integer ms value (there are 51.4 pulses in 2ms).
> >
> >One easy way to do it would be to generate 2 signals: the 25.7kHz
> >and the 2ms. You can the just put them through an AND or OR gate
> >(depending on the value you need for the idle state) and you get
> >your OOK signal. But there will be a very short pulse at the
> >beginning and at the end of each frequency pulse.
> >
> >Another way is quite similar, but you use a mod 51 prescaller and
> >use its output for the AND gate. You can even use the other timer to
> >do the prescaller (input to the timer the output frequency of 25.7kHz)
> >
> >Regards,
> >Michael K.
> >
> >--- In m...@yahoogroups.com, Vishal Kema wrote:
> > >
> > > Guys
> > > This might sound silly but I am trying to generate 25.7KHz
> > frequency signal from MSP430. The signal should be like this.
> > >
> > > 25.7KHz pulses for 2ms duration then stay off for another 2ms
> > duration. This keeps on repeating.
> > >
> > > I would need some suggestions on how to generate this kind of
> > signal. I have tried many things but failed.
> > >
> > > THanks!
> > >
> > >
> > >
> > > From cricket scores to your friends. Try the Yahoo! India
> > Homepage! http://in.yahoo.com/trynew
> > >
> > > [Non-text portions of this message have been removed]
> > >
> >
> >
> >
> >
> >------------------------------------
> >
> >
> >
> >



(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )