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Discussion Groups | MSP430 | XTAL - the oscillator
The purpose of this group is to foster exchange of information on the Texas Instruments MSP430 family of microcontrollers and related tools. Everyone welcome, all levels of familiarity/expertise.
XTAL - the oscillator - mike2forums - Nov 17 13:05:14 2009
Hello Forum members,
I am using MSP430F2618 with a XTAL of 1MHz connected to XT1 pins. The bus clock (MCLK) is 250KHz while the aux clock (ACLK) is 1MHz. I am using ACLK to different peripherals like UART, SPI, timer etc.
Is it possible that the timer execution will get affected as the MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK will be used to execute the instructions while ACLK will drive the peripheral.
I observed similar while working with the timer ISRs. I am using TI-MSP430FET(PIF) to debug my code having a timer ISR and updating the TBCCR0 and TBCCR1 registers. I observed a little difference in two register values when I put breakpoint in ISR. Is the debugger playing any role for timer execution?
I have read the datasheet where it is stated that some cpu cycles will be used to enter and exit the timer ISR. How is this affecting the timer counts?
Anyone having similar issues/observations.........?? Thanks in advance.
Mike
------------------------------------
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
I am using MSP430F2618 with a XTAL of 1MHz connected to XT1 pins. The bus clock (MCLK) is 250KHz while the aux clock (ACLK) is 1MHz. I am using ACLK to different peripherals like UART, SPI, timer etc.
Is it possible that the timer execution will get affected as the MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK will be used to execute the instructions while ACLK will drive the peripheral.
I observed similar while working with the timer ISRs. I am using TI-MSP430FET(PIF) to debug my code having a timer ISR and updating the TBCCR0 and TBCCR1 registers. I observed a little difference in two register values when I put breakpoint in ISR. Is the debugger playing any role for timer execution?
I have read the datasheet where it is stated that some cpu cycles will be used to enter and exit the timer ISR. How is this affecting the timer counts?
Anyone having similar issues/observations.........?? Thanks in advance.
Mike
------------------------------------
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
Re: XTAL - the oscillator - mike2forums - Nov 20 6:40:33 2009
Hello members,
Has anyone observed similar issues? haven't anyone used timer for PWM?
Any help........Thanks in advance.
Mike.
--- In m...@yahoogroups.com, "mike2forums" wrote:
>
> Hello Forum members,
>
> I am using MSP430F2618 with a XTAL of 1MHz connected to XT1 pins. The bus clock (MCLK) is 250KHz while the aux clock (ACLK) is 1MHz. I am using ACLK to different peripherals like UART, SPI, timer etc.
>
> Is it possible that the timer execution will get affected as the MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK will be used to execute the instructions while ACLK will drive the peripheral.
>
> I observed similar while working with the timer ISRs. I am using TI-MSP430FET(PIF) to debug my code having a timer ISR and updating the TBCCR0 and TBCCR1 registers. I observed a little difference in two register values when I put breakpoint in ISR. Is the debugger playing any role for timer execution?
>
> I have read the datasheet where it is stated that some cpu cycles will be used to enter and exit the timer ISR. How is this affecting the timer counts?
>
> Anyone having similar issues/observations.........?? Thanks in advance.
>
> Mike
>
------------------------------------
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
Has anyone observed similar issues? haven't anyone used timer for PWM?
Any help........Thanks in advance.
Mike.
--- In m...@yahoogroups.com, "mike2forums"
>
> Hello Forum members,
>
> I am using MSP430F2618 with a XTAL of 1MHz connected to XT1 pins. The bus clock (MCLK) is 250KHz while the aux clock (ACLK) is 1MHz. I am using ACLK to different peripherals like UART, SPI, timer etc.
>
> Is it possible that the timer execution will get affected as the MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK will be used to execute the instructions while ACLK will drive the peripheral.
>
> I observed similar while working with the timer ISRs. I am using TI-MSP430FET(PIF) to debug my code having a timer ISR and updating the TBCCR0 and TBCCR1 registers. I observed a little difference in two register values when I put breakpoint in ISR. Is the debugger playing any role for timer execution?
>
> I have read the datasheet where it is stated that some cpu cycles will be used to enter and exit the timer ISR. How is this affecting the timer counts?
>
> Anyone having similar issues/observations.........?? Thanks in advance.
>
> Mike
>
------------------------------------
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
Re: XTAL - the oscillator - old_cow_yellow - Nov 20 10:28:12 2009
Yes, I observed the same issue no matter what CPU I use. They all take one or more cycles
to do anything.
--- In m...@yahoogroups.com, "mike2forums" wrote:
>
> Hello members,
>
> Has anyone observed similar issues? haven't anyone used timer for PWM?
>
> Any help........Thanks in advance.
>
> Mike.
>
> --- In m...@yahoogroups.com, "mike2forums" wrote:
> >
> > Hello Forum members,
> >
> > I am using MSP430F2618 with a XTAL of 1MHz connected to XT1 pins. The bus clock (MCLK) is 250KHz while the aux clock (ACLK) is 1MHz. I am using ACLK to different peripherals like UART, SPI, timer etc.
> >
> > Is it possible that the timer execution will get affected as the MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK will be used to execute the instructions while ACLK will drive the peripheral.
> >
> > I observed similar while working with the timer ISRs. I am using TI-MSP430FET(PIF) to debug my code having a timer ISR and updating the TBCCR0 and TBCCR1 registers. I observed a little difference in two register values when I put breakpoint in ISR. Is the debugger playing any role for timer execution?
> >
> > I have read the datasheet where it is stated that some cpu cycles will be used to enter and exit the timer ISR. How is this affecting the timer counts?
> >
> > Anyone having similar issues/observations.........?? Thanks in advance.
> >
> > Mike
>
------------------------------------
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
--- In m...@yahoogroups.com, "mike2forums"
>
> Hello members,
>
> Has anyone observed similar issues? haven't anyone used timer for PWM?
>
> Any help........Thanks in advance.
>
> Mike.
>
> --- In m...@yahoogroups.com, "mike2forums"
> >
> > Hello Forum members,
> >
> > I am using MSP430F2618 with a XTAL of 1MHz connected to XT1 pins. The bus clock (MCLK) is 250KHz while the aux clock (ACLK) is 1MHz. I am using ACLK to different peripherals like UART, SPI, timer etc.
> >
> > Is it possible that the timer execution will get affected as the MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK will be used to execute the instructions while ACLK will drive the peripheral.
> >
> > I observed similar while working with the timer ISRs. I am using TI-MSP430FET(PIF) to debug my code having a timer ISR and updating the TBCCR0 and TBCCR1 registers. I observed a little difference in two register values when I put breakpoint in ISR. Is the debugger playing any role for timer execution?
> >
> > I have read the datasheet where it is stated that some cpu cycles will be used to enter and exit the timer ISR. How is this affecting the timer counts?
> >
> > Anyone having similar issues/observations.........?? Thanks in advance.
> >
> > Mike
>
------------------------------------
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
Re: XTAL - the oscillator - mike2forums - Nov 20 12:36:20 2009
What is the reason then? TI does not mention anything about this in datasheet. What is the
solution for this?
Any help.........Thanks in advance.
Mike.
--- In m...@yahoogroups.com, "old_cow_yellow" wrote:
>
> Yes, I observed the same issue no matter what CPU I use. They all take one or more cycles to do anything.
>
> --- In m...@yahoogroups.com, "mike2forums" wrote:
> >
> > Hello members,
> >
> > Has anyone observed similar issues? haven't anyone used timer for PWM?
> >
> > Any help........Thanks in advance.
> >
> > Mike.
> >
> > --- In m...@yahoogroups.com, "mike2forums" wrote:
> > >
> > > Hello Forum members,
> > >
> > > I am using MSP430F2618 with a XTAL of 1MHz connected to XT1 pins. The bus clock (MCLK) is 250KHz while the aux clock (ACLK) is 1MHz. I am using ACLK to different peripherals like UART, SPI, timer etc.
> > >
> > > Is it possible that the timer execution will get affected as the MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK will be used to execute the instructions while ACLK will drive the peripheral.
> > >
> > > I observed similar while working with the timer ISRs. I am using TI-MSP430FET(PIF) to debug my code having a timer ISR and updating the TBCCR0 and TBCCR1 registers. I observed a little difference in two register values when I put breakpoint in ISR. Is the debugger playing any role for timer execution?
> > >
> > > I have read the datasheet where it is stated that some cpu cycles will be used to enter and exit the timer ISR. How is this affecting the timer counts?
> > >
> > > Anyone having similar issues/observations.........?? Thanks in advance.
> > >
> > > Mike
> > >
>
------------------------------------
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
Any help.........Thanks in advance.
Mike.
--- In m...@yahoogroups.com, "old_cow_yellow"
>
> Yes, I observed the same issue no matter what CPU I use. They all take one or more cycles to do anything.
>
> --- In m...@yahoogroups.com, "mike2forums"
> >
> > Hello members,
> >
> > Has anyone observed similar issues? haven't anyone used timer for PWM?
> >
> > Any help........Thanks in advance.
> >
> > Mike.
> >
> > --- In m...@yahoogroups.com, "mike2forums"
> > >
> > > Hello Forum members,
> > >
> > > I am using MSP430F2618 with a XTAL of 1MHz connected to XT1 pins. The bus clock (MCLK) is 250KHz while the aux clock (ACLK) is 1MHz. I am using ACLK to different peripherals like UART, SPI, timer etc.
> > >
> > > Is it possible that the timer execution will get affected as the MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK will be used to execute the instructions while ACLK will drive the peripheral.
> > >
> > > I observed similar while working with the timer ISRs. I am using TI-MSP430FET(PIF) to debug my code having a timer ISR and updating the TBCCR0 and TBCCR1 registers. I observed a little difference in two register values when I put breakpoint in ISR. Is the debugger playing any role for timer execution?
> > >
> > > I have read the datasheet where it is stated that some cpu cycles will be used to enter and exit the timer ISR. How is this affecting the timer counts?
> > >
> > > Anyone having similar issues/observations.........?? Thanks in advance.
> > >
> > > Mike
> > >
>
------------------------------------
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
Re: Re: XTAL - the oscillator - OneStone - Nov 20 12:59:47 2009
Mike this is mentioned in the data sheets, in fact in the user guides.
It is given as a warning against potential timer misreads when user an
MCLK that is slower than the timer clock. In SLAU144E for example this
is a note in para 12.2.1. There used to be a better explanation in
earlier manuals, but this seems to be all you get now.
Al
mike2forums wrote:
> What is the reason then? TI does not mention anything about this in datasheet. What is the solution for this?
>
> Any help.........Thanks in advance.
>
> Mike.
>
> --- In m...@yahoogroups.com, "old_cow_yellow" wrote:
>> Yes, I observed the same issue no matter what CPU I use. They all take one or more cycles to do anything.
>>
>> --- In m...@yahoogroups.com, "mike2forums" wrote:
>>> Hello members,
>>>
>>> Has anyone observed similar issues? haven't anyone used timer for PWM?
>>>
>>> Any help........Thanks in advance.
>>>
>>> Mike.
>>>
>>> --- In m...@yahoogroups.com, "mike2forums" wrote:
>>>> Hello Forum members,
>>>>
>>>> I am using MSP430F2618 with a XTAL of 1MHz connected to XT1 pins. The bus clock (MCLK) is 250KHz while the aux clock (ACLK) is 1MHz. I am using ACLK to different peripherals like UART, SPI, timer etc.
>>>>
>>>> Is it possible that the timer execution will get affected as the MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK will be used to execute the instructions while ACLK will drive the peripheral.
>>>>
>>>> I observed similar while working with the timer ISRs. I am using TI-MSP430FET(PIF) to debug my code having a timer ISR and updating the TBCCR0 and TBCCR1 registers. I observed a little difference in two register values when I put breakpoint in ISR. Is the debugger playing any role for timer execution?
>>>>
>>>> I have read the datasheet where it is stated that some cpu cycles will be used to enter and exit the timer ISR. How is this affecting the timer counts?
>>>>
>>>> Anyone having similar issues/observations.........?? Thanks in advance.
>>>>
>>>> Mike
>>>>
> ------------------------------------
______________________________
controlSUITE™ software. Comprehensive. Intuitive. Optimized.
Real-world software for real-time control. Details Here!
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
It is given as a warning against potential timer misreads when user an
MCLK that is slower than the timer clock. In SLAU144E for example this
is a note in para 12.2.1. There used to be a better explanation in
earlier manuals, but this seems to be all you get now.
Al
mike2forums wrote:
> What is the reason then? TI does not mention anything about this in datasheet. What is the solution for this?
>
> Any help.........Thanks in advance.
>
> Mike.
>
> --- In m...@yahoogroups.com, "old_cow_yellow"
>> Yes, I observed the same issue no matter what CPU I use. They all take one or more cycles to do anything.
>>
>> --- In m...@yahoogroups.com, "mike2forums"
>>> Hello members,
>>>
>>> Has anyone observed similar issues? haven't anyone used timer for PWM?
>>>
>>> Any help........Thanks in advance.
>>>
>>> Mike.
>>>
>>> --- In m...@yahoogroups.com, "mike2forums"
>>>> Hello Forum members,
>>>>
>>>> I am using MSP430F2618 with a XTAL of 1MHz connected to XT1 pins. The bus clock (MCLK) is 250KHz while the aux clock (ACLK) is 1MHz. I am using ACLK to different peripherals like UART, SPI, timer etc.
>>>>
>>>> Is it possible that the timer execution will get affected as the MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK will be used to execute the instructions while ACLK will drive the peripheral.
>>>>
>>>> I observed similar while working with the timer ISRs. I am using TI-MSP430FET(PIF) to debug my code having a timer ISR and updating the TBCCR0 and TBCCR1 registers. I observed a little difference in two register values when I put breakpoint in ISR. Is the debugger playing any role for timer execution?
>>>>
>>>> I have read the datasheet where it is stated that some cpu cycles will be used to enter and exit the timer ISR. How is this affecting the timer counts?
>>>>
>>>> Anyone having similar issues/observations.........?? Thanks in advance.
>>>>
>>>> Mike
>>>>
> ------------------------------------
______________________________
controlSUITE™ software. Comprehensive. Intuitive. Optimized.
Real-world software for real-time control. Details Here!
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
Re: Re: XTAL - the oscillator - microbit_ubuntu_9101 - Nov 21 11:34:13 2009
I think you have to keep in mind that the timers can run on a different
clock than the CPU, ie. asynchronous.
Therefore it would make sense that there is at least 1 cycle of
propagation to allow for sync.
B rgds
Kris
On Fri, 2009-11-20 at 17:35 +0000, mike2forums wrote:
> What is the reason then? TI does not mention anything about this in datasheet. What is the solution for this?
>
> Any help.........Thanks in advance.
>
> Mike.
>
> --- In m...@yahoogroups.com, "old_cow_yellow" wrote:
> >
> > Yes, I observed the same issue no matter what CPU I use. They all take one or more cycles to do anything.
> >
> > --- In m...@yahoogroups.com, "mike2forums" wrote:
> > >
> > > Hello members,
> > >
> > > Has anyone observed similar issues? haven't anyone used timer for PWM?
> > >
> > > Any help........Thanks in advance.
> > >
> > > Mike.
> > >
> > > --- In m...@yahoogroups.com, "mike2forums" wrote:
> > > >
> > > > Hello Forum members,
> > > >
> > > > I am using MSP430F2618 with a XTAL of 1MHz connected to XT1 pins. The bus clock (MCLK) is 250KHz while the aux clock (ACLK) is 1MHz. I am using ACLK to different peripherals like UART, SPI, timer etc.
> > > >
> > > > Is it possible that the timer execution will get affected as the MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK will be used to execute the instructions while ACLK will drive the peripheral.
> > > >
> > > > I observed similar while working with the timer ISRs. I am using TI-MSP430FET(PIF) to debug my code having a timer ISR and updating the TBCCR0 and TBCCR1 registers. I observed a little difference in two register values when I put breakpoint in ISR. Is the debugger playing any role for timer execution?
> > > >
> > > > I have read the datasheet where it is stated that some cpu cycles will be used to enter and exit the timer ISR. How is this affecting the timer counts?
> > > >
> > > > Anyone having similar issues/observations.........?? Thanks in advance.
> > > >
> > > > Mike
> > > >
> > >
> >
> ------------------------------------
______________________________
controlSUITE™ software. Comprehensive. Intuitive. Optimized.
Real-world software for real-time control. Details Here!
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
clock than the CPU, ie. asynchronous.
Therefore it would make sense that there is at least 1 cycle of
propagation to allow for sync.
B rgds
Kris
On Fri, 2009-11-20 at 17:35 +0000, mike2forums wrote:
> What is the reason then? TI does not mention anything about this in datasheet. What is the solution for this?
>
> Any help.........Thanks in advance.
>
> Mike.
>
> --- In m...@yahoogroups.com, "old_cow_yellow"
> >
> > Yes, I observed the same issue no matter what CPU I use. They all take one or more cycles to do anything.
> >
> > --- In m...@yahoogroups.com, "mike2forums"
> > >
> > > Hello members,
> > >
> > > Has anyone observed similar issues? haven't anyone used timer for PWM?
> > >
> > > Any help........Thanks in advance.
> > >
> > > Mike.
> > >
> > > --- In m...@yahoogroups.com, "mike2forums"
> > > >
> > > > Hello Forum members,
> > > >
> > > > I am using MSP430F2618 with a XTAL of 1MHz connected to XT1 pins. The bus clock (MCLK) is 250KHz while the aux clock (ACLK) is 1MHz. I am using ACLK to different peripherals like UART, SPI, timer etc.
> > > >
> > > > Is it possible that the timer execution will get affected as the MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK will be used to execute the instructions while ACLK will drive the peripheral.
> > > >
> > > > I observed similar while working with the timer ISRs. I am using TI-MSP430FET(PIF) to debug my code having a timer ISR and updating the TBCCR0 and TBCCR1 registers. I observed a little difference in two register values when I put breakpoint in ISR. Is the debugger playing any role for timer execution?
> > > >
> > > > I have read the datasheet where it is stated that some cpu cycles will be used to enter and exit the timer ISR. How is this affecting the timer counts?
> > > >
> > > > Anyone having similar issues/observations.........?? Thanks in advance.
> > > >
> > > > Mike
> > > >
> > >
> >
> ------------------------------------
______________________________
controlSUITE™ software. Comprehensive. Intuitive. Optimized.
Real-world software for real-time control. Details Here!
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
Re: Re: XTAL - the oscillator - microbit_ubuntu_9101 - Nov 21 11:43:18 2009
I forgot to also mention that it's possible the timer(s) are ripple
counters (this is conjecture however).
When I used F149 in the early days, the issue of reading the timer twice
(or till correct) - or stopping the timer while reading - wasn't
documented at all.
It took me 2 full days to find my "bug" (well, accounting for "catching
it"). Every ~ 1 million reads BIT4 on TAR would read as 0 when it was
actually a 1.
Therefore I think - if it indeed is a ripple counter - there might be a
cycle there somewhere too.
I thought about this a long time ago, if the TAR/TBR is a synchronous
counter design, _all_ bits should update within the same clock cycle....
HTH
B rgds
Kris
On Sun, 2009-11-22 at 03:34 +1100, microbit_ubuntu_9101 wrote:
> I think you have to keep in mind that the timers can run on a different
> clock than the CPU, ie. asynchronous.
> Therefore it would make sense that there is at least 1 cycle of
> propagation to allow for sync.
>
> B rgds
> Kris
>
> On Fri, 2009-11-20 at 17:35 +0000, mike2forums wrote:
> > What is the reason then? TI does not mention anything about this in datasheet. What is the solution for this?
> >
> > Any help.........Thanks in advance.
> >
> > Mike.
> >
> > --- In m...@yahoogroups.com, "old_cow_yellow" wrote:
> > >
> > > Yes, I observed the same issue no matter what CPU I use. They all take one or more cycles to do anything.
> > >
> > > --- In m...@yahoogroups.com, "mike2forums" wrote:
> > > >
> > > > Hello members,
> > > >
> > > > Has anyone observed similar issues? haven't anyone used timer for PWM?
> > > >
> > > > Any help........Thanks in advance.
> > > >
> > > > Mike.
> > > >
> > > > --- In m...@yahoogroups.com, "mike2forums" wrote:
> > > > >
> > > > > Hello Forum members,
> > > > >
> > > > > I am using MSP430F2618 with a XTAL of 1MHz connected to XT1 pins. The bus clock (MCLK) is 250KHz while the aux clock (ACLK) is 1MHz. I am using ACLK to different peripherals like UART, SPI, timer etc.
> > > > >
> > > > > Is it possible that the timer execution will get affected as the MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK will be used to execute the instructions while ACLK will drive the peripheral.
> > > > >
> > > > > I observed similar while working with the timer ISRs. I am using TI-MSP430FET(PIF) to debug my code having a timer ISR and updating the TBCCR0 and TBCCR1 registers. I observed a little difference in two register values when I put breakpoint in ISR. Is the debugger playing any role for timer execution?
> > > > >
> > > > > I have read the datasheet where it is stated that some cpu cycles will be used to enter and exit the timer ISR. How is this affecting the timer counts?
> > > > >
> > > > > Anyone having similar issues/observations.........?? Thanks in advance.
> > > > >
> > > > > Mike
> > > > >
> > > >
> > >
> >
> >
> >
> >
> > ------------------------------------
> >
> >
> >
> >
______________________________
controlSUITE™ software. Comprehensive. Intuitive. Optimized.
Real-world software for real-time control. Details Here!
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
counters (this is conjecture however).
When I used F149 in the early days, the issue of reading the timer twice
(or till correct) - or stopping the timer while reading - wasn't
documented at all.
It took me 2 full days to find my "bug" (well, accounting for "catching
it"). Every ~ 1 million reads BIT4 on TAR would read as 0 when it was
actually a 1.
Therefore I think - if it indeed is a ripple counter - there might be a
cycle there somewhere too.
I thought about this a long time ago, if the TAR/TBR is a synchronous
counter design, _all_ bits should update within the same clock cycle....
HTH
B rgds
Kris
On Sun, 2009-11-22 at 03:34 +1100, microbit_ubuntu_9101 wrote:
> I think you have to keep in mind that the timers can run on a different
> clock than the CPU, ie. asynchronous.
> Therefore it would make sense that there is at least 1 cycle of
> propagation to allow for sync.
>
> B rgds
> Kris
>
> On Fri, 2009-11-20 at 17:35 +0000, mike2forums wrote:
> > What is the reason then? TI does not mention anything about this in datasheet. What is the solution for this?
> >
> > Any help.........Thanks in advance.
> >
> > Mike.
> >
> > --- In m...@yahoogroups.com, "old_cow_yellow"
> > >
> > > Yes, I observed the same issue no matter what CPU I use. They all take one or more cycles to do anything.
> > >
> > > --- In m...@yahoogroups.com, "mike2forums"
> > > >
> > > > Hello members,
> > > >
> > > > Has anyone observed similar issues? haven't anyone used timer for PWM?
> > > >
> > > > Any help........Thanks in advance.
> > > >
> > > > Mike.
> > > >
> > > > --- In m...@yahoogroups.com, "mike2forums"
> > > > >
> > > > > Hello Forum members,
> > > > >
> > > > > I am using MSP430F2618 with a XTAL of 1MHz connected to XT1 pins. The bus clock (MCLK) is 250KHz while the aux clock (ACLK) is 1MHz. I am using ACLK to different peripherals like UART, SPI, timer etc.
> > > > >
> > > > > Is it possible that the timer execution will get affected as the MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK will be used to execute the instructions while ACLK will drive the peripheral.
> > > > >
> > > > > I observed similar while working with the timer ISRs. I am using TI-MSP430FET(PIF) to debug my code having a timer ISR and updating the TBCCR0 and TBCCR1 registers. I observed a little difference in two register values when I put breakpoint in ISR. Is the debugger playing any role for timer execution?
> > > > >
> > > > > I have read the datasheet where it is stated that some cpu cycles will be used to enter and exit the timer ISR. How is this affecting the timer counts?
> > > > >
> > > > > Anyone having similar issues/observations.........?? Thanks in advance.
> > > > >
> > > > > Mike
> > > > >
> > > >
> > >
> >
> >
> >
> >
> > ------------------------------------
> >
> >
> >
> >
______________________________
controlSUITE™ software. Comprehensive. Intuitive. Optimized.
Real-world software for real-time control. Details Here!
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
Re: XTAL - the oscillator - mike2forums - Nov 23 10:28:44 2009
Whether TI agrees this? This is a major restriction on using timer or any other peripheral
at higher clocks. By the way, can this happen to any other MSP430 peripheral?
Mike.
--- In m...@yahoogroups.com, microbit_ubuntu_9101 wrote:
>
> I forgot to also mention that it's possible the timer(s) are ripple
> counters (this is conjecture however).
> When I used F149 in the early days, the issue of reading the timer twice
> (or till correct) - or stopping the timer while reading - wasn't
> documented at all.
> It took me 2 full days to find my "bug" (well, accounting for "catching
> it"). Every ~ 1 million reads BIT4 on TAR would read as 0 when it was
> actually a 1.
> Therefore I think - if it indeed is a ripple counter - there might be a
> cycle there somewhere too.
> I thought about this a long time ago, if the TAR/TBR is a synchronous
> counter design, _all_ bits should update within the same clock cycle....
>
> HTH
> B rgds
> Kris
> On Sun, 2009-11-22 at 03:34 +1100, microbit_ubuntu_9101 wrote:
> > I think you have to keep in mind that the timers can run on a different
> > clock than the CPU, ie. asynchronous.
> > Therefore it would make sense that there is at least 1 cycle of
> > propagation to allow for sync.
> >
> > B rgds
> > Kris
> >
> > On Fri, 2009-11-20 at 17:35 +0000, mike2forums wrote:
> > > What is the reason then? TI does not mention anything about this in datasheet. What is the solution for this?
> > >
> > > Any help.........Thanks in advance.
> > >
> > > Mike.
> > >
> > > --- In m...@yahoogroups.com, "old_cow_yellow" wrote:
> > > >
> > > > Yes, I observed the same issue no matter what CPU I use. They all take one or more cycles to do anything.
> > > >
> > > > --- In m...@yahoogroups.com, "mike2forums" wrote:
> > > > >
> > > > > Hello members,
> > > > >
> > > > > Has anyone observed similar issues? haven't anyone used timer for PWM?
> > > > >
> > > > > Any help........Thanks in advance.
> > > > >
> > > > > Mike.
> > > > >
> > > > > --- In m...@yahoogroups.com, "mike2forums" wrote:
> > > > > >
> > > > > > Hello Forum members,
> > > > > >
> > > > > > I am using MSP430F2618 with a XTAL of 1MHz connected to XT1 pins. The bus clock (MCLK) is 250KHz while the aux clock (ACLK) is 1MHz. I am using ACLK to different peripherals like UART, SPI, timer etc.
> > > > > >
> > > > > > Is it possible that the timer execution will get affected as the MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK will be used to execute the instructions while ACLK will drive the peripheral.
> > > > > >
> > > > > > I observed similar while working with the timer ISRs. I am using TI-MSP430FET(PIF) to debug my code having a timer ISR and updating the TBCCR0 and TBCCR1 registers. I observed a little difference in two register values when I put breakpoint in ISR. Is the debugger playing any role for timer execution?
> > > > > >
> > > > > > I have read the datasheet where it is stated that some cpu cycles will be used to enter and exit the timer ISR. How is this affecting the timer counts?
> > > > > >
> > > > > > Anyone having similar issues/observations.........?? Thanks in advance.
> > > > > >
> > > > > > Mike
> > > > > >
> > > > >
> > > >
> > >
> > >
> > >
> > >
> > > ------------------------------------
> > >
> > >
> > >
> > >
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
Mike.
--- In m...@yahoogroups.com, microbit_ubuntu_9101
>
> I forgot to also mention that it's possible the timer(s) are ripple
> counters (this is conjecture however).
> When I used F149 in the early days, the issue of reading the timer twice
> (or till correct) - or stopping the timer while reading - wasn't
> documented at all.
> It took me 2 full days to find my "bug" (well, accounting for "catching
> it"). Every ~ 1 million reads BIT4 on TAR would read as 0 when it was
> actually a 1.
> Therefore I think - if it indeed is a ripple counter - there might be a
> cycle there somewhere too.
> I thought about this a long time ago, if the TAR/TBR is a synchronous
> counter design, _all_ bits should update within the same clock cycle....
>
> HTH
> B rgds
> Kris
> On Sun, 2009-11-22 at 03:34 +1100, microbit_ubuntu_9101 wrote:
> > I think you have to keep in mind that the timers can run on a different
> > clock than the CPU, ie. asynchronous.
> > Therefore it would make sense that there is at least 1 cycle of
> > propagation to allow for sync.
> >
> > B rgds
> > Kris
> >
> > On Fri, 2009-11-20 at 17:35 +0000, mike2forums wrote:
> > > What is the reason then? TI does not mention anything about this in datasheet. What is the solution for this?
> > >
> > > Any help.........Thanks in advance.
> > >
> > > Mike.
> > >
> > > --- In m...@yahoogroups.com, "old_cow_yellow"
> > > >
> > > > Yes, I observed the same issue no matter what CPU I use. They all take one or more cycles to do anything.
> > > >
> > > > --- In m...@yahoogroups.com, "mike2forums"
> > > > >
> > > > > Hello members,
> > > > >
> > > > > Has anyone observed similar issues? haven't anyone used timer for PWM?
> > > > >
> > > > > Any help........Thanks in advance.
> > > > >
> > > > > Mike.
> > > > >
> > > > > --- In m...@yahoogroups.com, "mike2forums"
> > > > > >
> > > > > > Hello Forum members,
> > > > > >
> > > > > > I am using MSP430F2618 with a XTAL of 1MHz connected to XT1 pins. The bus clock (MCLK) is 250KHz while the aux clock (ACLK) is 1MHz. I am using ACLK to different peripherals like UART, SPI, timer etc.
> > > > > >
> > > > > > Is it possible that the timer execution will get affected as the MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK will be used to execute the instructions while ACLK will drive the peripheral.
> > > > > >
> > > > > > I observed similar while working with the timer ISRs. I am using TI-MSP430FET(PIF) to debug my code having a timer ISR and updating the TBCCR0 and TBCCR1 registers. I observed a little difference in two register values when I put breakpoint in ISR. Is the debugger playing any role for timer execution?
> > > > > >
> > > > > > I have read the datasheet where it is stated that some cpu cycles will be used to enter and exit the timer ISR. How is this affecting the timer counts?
> > > > > >
> > > > > > Anyone having similar issues/observations.........?? Thanks in advance.
> > > > > >
> > > > > > Mike
> > > > > >
> > > > >
> > > >
> > >
> > >
> > >
> > >
> > > ------------------------------------
> > >
> > >
> > >
> > >
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
Re: XTAL - the oscillator - mike2forums - Nov 23 10:33:43 2009
Hi OneStone,
It is applicable if the timer clock is asynchronous to CPU clock..similar to SCS bit, is there any option available?
Mike.
--- In m...@yahoogroups.com, OneStone wrote:
>
> Mike this is mentioned in the data sheets, in fact in the user guides.
> It is given as a warning against potential timer misreads when user an
> MCLK that is slower than the timer clock. In SLAU144E for example this
> is a note in para 12.2.1. There used to be a better explanation in
> earlier manuals, but this seems to be all you get now.
>
> Al
>
> mike2forums wrote:
> > What is the reason then? TI does not mention anything about this in datasheet. What is the solution for this?
> >
> > Any help.........Thanks in advance.
> >
> > Mike.
> >
> > --- In m...@yahoogroups.com, "old_cow_yellow" wrote:
> >> Yes, I observed the same issue no matter what CPU I use. They all take one or more cycles to do anything.
> >>
> >> --- In m...@yahoogroups.com, "mike2forums" wrote:
> >>> Hello members,
> >>>
> >>> Has anyone observed similar issues? haven't anyone used timer for PWM?
> >>>
> >>> Any help........Thanks in advance.
> >>>
> >>> Mike.
> >>>
> >>> --- In m...@yahoogroups.com, "mike2forums" wrote:
> >>>> Hello Forum members,
> >>>>
> >>>> I am using MSP430F2618 with a XTAL of 1MHz connected to XT1 pins. The bus clock (MCLK) is 250KHz while the aux clock (ACLK) is 1MHz. I am using ACLK to different peripherals like UART, SPI, timer etc.
> >>>>
> >>>> Is it possible that the timer execution will get affected as the MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK will be used to execute the instructions while ACLK will drive the peripheral.
> >>>>
> >>>> I observed similar while working with the timer ISRs. I am using TI-MSP430FET(PIF) to debug my code having a timer ISR and updating the TBCCR0 and TBCCR1 registers. I observed a little difference in two register values when I put breakpoint in ISR. Is the debugger playing any role for timer execution?
> >>>>
> >>>> I have read the datasheet where it is stated that some cpu cycles will be used to enter and exit the timer ISR. How is this affecting the timer counts?
> >>>>
> >>>> Anyone having similar issues/observations.........?? Thanks in advance.
> >>>>
> >>>> Mike
> >>>>
> >
> >
> >
> >
> > ------------------------------------
> >
> >
> >
> >
______________________________
controlSUITE™ software. Comprehensive. Intuitive. Optimized.
Real-world software for real-time control. Details Here!
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
It is applicable if the timer clock is asynchronous to CPU clock..similar to SCS bit, is there any option available?
Mike.
--- In m...@yahoogroups.com, OneStone
>
> Mike this is mentioned in the data sheets, in fact in the user guides.
> It is given as a warning against potential timer misreads when user an
> MCLK that is slower than the timer clock. In SLAU144E for example this
> is a note in para 12.2.1. There used to be a better explanation in
> earlier manuals, but this seems to be all you get now.
>
> Al
>
> mike2forums wrote:
> > What is the reason then? TI does not mention anything about this in datasheet. What is the solution for this?
> >
> > Any help.........Thanks in advance.
> >
> > Mike.
> >
> > --- In m...@yahoogroups.com, "old_cow_yellow"
> >> Yes, I observed the same issue no matter what CPU I use. They all take one or more cycles to do anything.
> >>
> >> --- In m...@yahoogroups.com, "mike2forums"
> >>> Hello members,
> >>>
> >>> Has anyone observed similar issues? haven't anyone used timer for PWM?
> >>>
> >>> Any help........Thanks in advance.
> >>>
> >>> Mike.
> >>>
> >>> --- In m...@yahoogroups.com, "mike2forums"
> >>>> Hello Forum members,
> >>>>
> >>>> I am using MSP430F2618 with a XTAL of 1MHz connected to XT1 pins. The bus clock (MCLK) is 250KHz while the aux clock (ACLK) is 1MHz. I am using ACLK to different peripherals like UART, SPI, timer etc.
> >>>>
> >>>> Is it possible that the timer execution will get affected as the MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK will be used to execute the instructions while ACLK will drive the peripheral.
> >>>>
> >>>> I observed similar while working with the timer ISRs. I am using TI-MSP430FET(PIF) to debug my code having a timer ISR and updating the TBCCR0 and TBCCR1 registers. I observed a little difference in two register values when I put breakpoint in ISR. Is the debugger playing any role for timer execution?
> >>>>
> >>>> I have read the datasheet where it is stated that some cpu cycles will be used to enter and exit the timer ISR. How is this affecting the timer counts?
> >>>>
> >>>> Anyone having similar issues/observations.........?? Thanks in advance.
> >>>>
> >>>> Mike
> >>>>
> >
> >
> >
> >
> > ------------------------------------
> >
> >
> >
> >
______________________________
controlSUITE™ software. Comprehensive. Intuitive. Optimized.
Real-world software for real-time control. Details Here!
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
Re: XTAL - the oscillator - Michael - Nov 23 11:06:29 2009
Mike,
Regardless of where the discussion has evolved to, let me say this:
> Is it possible that the timer execution will get affected as the
> MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK
> will be used to execute the instructions while ACLK will drive the
> peripheral.
You can even stop MCLK (by entering LPM for example) and the timer will continue to work.
> I observed similar while working with the timer ISRs. I am using
> TI-MSP430FET(PIF) to debug my code having a timer ISR and updating
> the TBCCR0 and TBCCR1 registers. I observed a little difference in
> two register values when I put breakpoint in ISR. Is the debugger
> playing any role for timer execution?
You are way too vague on this. I can think of a number of different interpretations of what you wrote, each with a different explanation so you will need to be much more precise when explaining what you did and what you found/what your results were.
> I have read the datasheet where it is stated that some cpu cycles
> will be used to enter and exit the timer ISR. How is this affecting
> the timer counts?
It won't affect the timer count, but it might/will affect your program flow. I don't know what you are trying to do with your timer or in the ISR, so there is nothing more to tell.
This might not relate to your problem, but I can tell you I've used a timer INCLK to measure a frequency signal of up to 80MHz using the internal 1:8 prescaller. The MSP showed the same frequency as a frequency counter connected in parallel to the same signal (taking ppm accuracy into account).
Regards,
Michael K.
--- In m...@yahoogroups.com, "mike2forums" wrote:
>
> Hello Forum members,
>
> I am using MSP430F2618 with a XTAL of 1MHz connected to XT1 pins. The bus clock (MCLK) is 250KHz while the aux clock (ACLK) is 1MHz. I am using ACLK to different peripherals like UART, SPI, timer etc.
>
> Is it possible that the timer execution will get affected as the MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK will be used to execute the instructions while ACLK will drive the peripheral.
>
> I observed similar while working with the timer ISRs. I am using TI-MSP430FET(PIF) to debug my code having a timer ISR and updating the TBCCR0 and TBCCR1 registers. I observed a little difference in two register values when I put breakpoint in ISR. Is the debugger playing any role for timer execution?
>
> I have read the datasheet where it is stated that some cpu cycles will be used to enter and exit the timer ISR. How is this affecting the timer counts?
>
> Anyone having similar issues/observations.........?? Thanks in advance.
>
> Mike
>
------------------------------------
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
Regardless of where the discussion has evolved to, let me say this:
> Is it possible that the timer execution will get affected as the
> MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK
> will be used to execute the instructions while ACLK will drive the
> peripheral.
You can even stop MCLK (by entering LPM for example) and the timer will continue to work.
> I observed similar while working with the timer ISRs. I am using
> TI-MSP430FET(PIF) to debug my code having a timer ISR and updating
> the TBCCR0 and TBCCR1 registers. I observed a little difference in
> two register values when I put breakpoint in ISR. Is the debugger
> playing any role for timer execution?
You are way too vague on this. I can think of a number of different interpretations of what you wrote, each with a different explanation so you will need to be much more precise when explaining what you did and what you found/what your results were.
> I have read the datasheet where it is stated that some cpu cycles
> will be used to enter and exit the timer ISR. How is this affecting
> the timer counts?
It won't affect the timer count, but it might/will affect your program flow. I don't know what you are trying to do with your timer or in the ISR, so there is nothing more to tell.
This might not relate to your problem, but I can tell you I've used a timer INCLK to measure a frequency signal of up to 80MHz using the internal 1:8 prescaller. The MSP showed the same frequency as a frequency counter connected in parallel to the same signal (taking ppm accuracy into account).
Regards,
Michael K.
--- In m...@yahoogroups.com, "mike2forums"
>
> Hello Forum members,
>
> I am using MSP430F2618 with a XTAL of 1MHz connected to XT1 pins. The bus clock (MCLK) is 250KHz while the aux clock (ACLK) is 1MHz. I am using ACLK to different peripherals like UART, SPI, timer etc.
>
> Is it possible that the timer execution will get affected as the MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK will be used to execute the instructions while ACLK will drive the peripheral.
>
> I observed similar while working with the timer ISRs. I am using TI-MSP430FET(PIF) to debug my code having a timer ISR and updating the TBCCR0 and TBCCR1 registers. I observed a little difference in two register values when I put breakpoint in ISR. Is the debugger playing any role for timer execution?
>
> I have read the datasheet where it is stated that some cpu cycles will be used to enter and exit the timer ISR. How is this affecting the timer counts?
>
> Anyone having similar issues/observations.........?? Thanks in advance.
>
> Mike
>
------------------------------------
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
Re: Re: XTAL - the oscillator - microbit_ubuntu_9101 - Nov 23 12:13:08 2009
Hi Mike,
I don't know about the ripple counter conjecture, I never followed it up
further.
It was actually TI that helped me out with the cause of "the bug" back
in 2000 (this wasn't documented back then - I knew what was happening
but didn't know _why_). I emailed with one of the original designers of
the MSP430 in Freising, Germany. They were very helpful and put me back
on track.
I was using the F149 in a 1.5 Mbps RF network that was freq hopping at
near Bluetooth timeslots (~650 uS IIRC). The timer was instrumental in
the TDMA operation, hence the *occasional* failures I was observing.
I'm not aware of any other peripherals that might need this precaution.
(unless something is asynchronously clocked while it is explicitly used
in a synchronous manner, I guess).
I don't understand your concern about using (relatively) high clock
speeds for timer compared to MCLK. Surely, anything that requires much
higher clocks on TAR/TBR will require proper throughput on CPU ?
What's the point otherwise.
Note that when using the same clock source for timer and MCLK (even when
prescaled) this isn't an issue then - clocks are synced anyway.
-- Kris
On Mon, 2009-11-23 at 15:26 +0000, mike2forums wrote:
> Whether TI agrees this? This is a major restriction on using timer or any other peripheral at higher clocks. By the way, can this happen to any other MSP430 peripheral?
>
> Mike.
>
> --- In m...@yahoogroups.com, microbit_ubuntu_9101 wrote:
> >
> > I forgot to also mention that it's possible the timer(s) are ripple
> > counters (this is conjecture however).
> > When I used F149 in the early days, the issue of reading the timer twice
> > (or till correct) - or stopping the timer while reading - wasn't
> > documented at all.
> > It took me 2 full days to find my "bug" (well, accounting for "catching
> > it"). Every ~ 1 million reads BIT4 on TAR would read as 0 when it was
> > actually a 1.
> > Therefore I think - if it indeed is a ripple counter - there might be a
> > cycle there somewhere too.
> > I thought about this a long time ago, if the TAR/TBR is a synchronous
> > counter design, _all_ bits should update within the same clock cycle....
> >
> > HTH
> > B rgds
> > Kris
> >
> >
> > On Sun, 2009-11-22 at 03:34 +1100, microbit_ubuntu_9101 wrote:
> > > I think you have to keep in mind that the timers can run on a different
> > > clock than the CPU, ie. asynchronous.
> > > Therefore it would make sense that there is at least 1 cycle of
> > > propagation to allow for sync.
> > >
> > > B rgds
> > > Kris
> > >
> > > On Fri, 2009-11-20 at 17:35 +0000, mike2forums wrote:
> > > > What is the reason then? TI does not mention anything about this in datasheet. What is the solution for this?
> > > >
> > > > Any help.........Thanks in advance.
> > > >
> > > > Mike.
> > > >
> > > > --- In m...@yahoogroups.com, "old_cow_yellow" wrote:
> > > > >
> > > > > Yes, I observed the same issue no matter what CPU I use. They all take one or more cycles to do anything.
> > > > >
> > > > > --- In m...@yahoogroups.com, "mike2forums" wrote:
> > > > > >
> > > > > > Hello members,
> > > > > >
> > > > > > Has anyone observed similar issues? haven't anyone used timer for PWM?
> > > > > >
> > > > > > Any help........Thanks in advance.
> > > > > >
> > > > > > Mike.
> > > > > >
> > > > > > --- In m...@yahoogroups.com, "mike2forums" wrote:
> > > > > > >
> > > > > > > Hello Forum members,
> > > > > > >
> > > > > > > I am using MSP430F2618 with a XTAL of 1MHz connected to XT1 pins. The bus clock (MCLK) is 250KHz while the aux clock (ACLK) is 1MHz. I am using ACLK to different peripherals like UART, SPI, timer etc.
> > > > > > >
> > > > > > > Is it possible that the timer execution will get affected as the MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK will be used to execute the instructions while ACLK will drive the peripheral.
> > > > > > >
> > > > > > > I observed similar while working with the timer ISRs. I am using TI-MSP430FET(PIF) to debug my code having a timer ISR and updating the TBCCR0 and TBCCR1 registers. I observed a little difference in two register values when I put breakpoint in ISR. Is the debugger playing any role for timer execution?
> > > > > > >
> > > > > > > I have read the datasheet where it is stated that some cpu cycles will be used to enter and exit the timer ISR. How is this affecting the timer counts?
> > > > > > >
> > > > > > > Anyone having similar issues/observations.........?? Thanks in advance.
> > > > > > >
> > > > > > > Mike
> > > > > > >
> > > > > >
> > > > >
> > > >
> > > >
> > > >
> > > >
> > > > ------------------------------------
> > > >
> > > >
> > > >
> > > >
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
I don't know about the ripple counter conjecture, I never followed it up
further.
It was actually TI that helped me out with the cause of "the bug" back
in 2000 (this wasn't documented back then - I knew what was happening
but didn't know _why_). I emailed with one of the original designers of
the MSP430 in Freising, Germany. They were very helpful and put me back
on track.
I was using the F149 in a 1.5 Mbps RF network that was freq hopping at
near Bluetooth timeslots (~650 uS IIRC). The timer was instrumental in
the TDMA operation, hence the *occasional* failures I was observing.
I'm not aware of any other peripherals that might need this precaution.
(unless something is asynchronously clocked while it is explicitly used
in a synchronous manner, I guess).
I don't understand your concern about using (relatively) high clock
speeds for timer compared to MCLK. Surely, anything that requires much
higher clocks on TAR/TBR will require proper throughput on CPU ?
What's the point otherwise.
Note that when using the same clock source for timer and MCLK (even when
prescaled) this isn't an issue then - clocks are synced anyway.
-- Kris
On Mon, 2009-11-23 at 15:26 +0000, mike2forums wrote:
> Whether TI agrees this? This is a major restriction on using timer or any other peripheral at higher clocks. By the way, can this happen to any other MSP430 peripheral?
>
> Mike.
>
> --- In m...@yahoogroups.com, microbit_ubuntu_9101
> >
> > I forgot to also mention that it's possible the timer(s) are ripple
> > counters (this is conjecture however).
> > When I used F149 in the early days, the issue of reading the timer twice
> > (or till correct) - or stopping the timer while reading - wasn't
> > documented at all.
> > It took me 2 full days to find my "bug" (well, accounting for "catching
> > it"). Every ~ 1 million reads BIT4 on TAR would read as 0 when it was
> > actually a 1.
> > Therefore I think - if it indeed is a ripple counter - there might be a
> > cycle there somewhere too.
> > I thought about this a long time ago, if the TAR/TBR is a synchronous
> > counter design, _all_ bits should update within the same clock cycle....
> >
> > HTH
> > B rgds
> > Kris
> >
> >
> > On Sun, 2009-11-22 at 03:34 +1100, microbit_ubuntu_9101 wrote:
> > > I think you have to keep in mind that the timers can run on a different
> > > clock than the CPU, ie. asynchronous.
> > > Therefore it would make sense that there is at least 1 cycle of
> > > propagation to allow for sync.
> > >
> > > B rgds
> > > Kris
> > >
> > > On Fri, 2009-11-20 at 17:35 +0000, mike2forums wrote:
> > > > What is the reason then? TI does not mention anything about this in datasheet. What is the solution for this?
> > > >
> > > > Any help.........Thanks in advance.
> > > >
> > > > Mike.
> > > >
> > > > --- In m...@yahoogroups.com, "old_cow_yellow"
> > > > >
> > > > > Yes, I observed the same issue no matter what CPU I use. They all take one or more cycles to do anything.
> > > > >
> > > > > --- In m...@yahoogroups.com, "mike2forums"
> > > > > >
> > > > > > Hello members,
> > > > > >
> > > > > > Has anyone observed similar issues? haven't anyone used timer for PWM?
> > > > > >
> > > > > > Any help........Thanks in advance.
> > > > > >
> > > > > > Mike.
> > > > > >
> > > > > > --- In m...@yahoogroups.com, "mike2forums"
> > > > > > >
> > > > > > > Hello Forum members,
> > > > > > >
> > > > > > > I am using MSP430F2618 with a XTAL of 1MHz connected to XT1 pins. The bus clock (MCLK) is 250KHz while the aux clock (ACLK) is 1MHz. I am using ACLK to different peripherals like UART, SPI, timer etc.
> > > > > > >
> > > > > > > Is it possible that the timer execution will get affected as the MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK will be used to execute the instructions while ACLK will drive the peripheral.
> > > > > > >
> > > > > > > I observed similar while working with the timer ISRs. I am using TI-MSP430FET(PIF) to debug my code having a timer ISR and updating the TBCCR0 and TBCCR1 registers. I observed a little difference in two register values when I put breakpoint in ISR. Is the debugger playing any role for timer execution?
> > > > > > >
> > > > > > > I have read the datasheet where it is stated that some cpu cycles will be used to enter and exit the timer ISR. How is this affecting the timer counts?
> > > > > > >
> > > > > > > Anyone having similar issues/observations.........?? Thanks in advance.
> > > > > > >
> > > > > > > Mike
> > > > > > >
> > > > > >
> > > > >
> > > >
> > > >
> > > >
> > > >
> > > > ------------------------------------
> > > >
> > > >
> > > >
> > > >
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
Re: Re: XTAL - the oscillator - OneStone - Nov 23 13:48:01 2009
Hi Mike I believe that it is also applicable to synchronous clocks where
the MCLK is slower than the ACLK, and I also believe it only affects the
timers, but it has been very long time since I looked and it seems to
be one of those things that has drifted out of the data sheets over time.
Not 100% sure, just have strong recollections of seeing some notes on it
many years ago.
Al
mike2forums wrote:
> Hi OneStone,
>
> It is applicable if the timer clock is asynchronous to CPU clock..similar to SCS bit, is there any option available?
>
> Mike.
> --- In m...@yahoogroups.com, OneStone wrote:
>> Mike this is mentioned in the data sheets, in fact in the user guides.
>> It is given as a warning against potential timer misreads when user an
>> MCLK that is slower than the timer clock. In SLAU144E for example this
>> is a note in para 12.2.1. There used to be a better explanation in
>> earlier manuals, but this seems to be all you get now.
>>
>> Al
>>
>> mike2forums wrote:
>>> What is the reason then? TI does not mention anything about this in datasheet. What is the solution for this?
>>>
>>> Any help.........Thanks in advance.
>>>
>>> Mike.
>>>
>>> --- In m...@yahoogroups.com, "old_cow_yellow" wrote:
>>>> Yes, I observed the same issue no matter what CPU I use. They all take one or more cycles to do anything.
>>>>
>>>> --- In m...@yahoogroups.com, "mike2forums" wrote:
>>>>> Hello members,
>>>>>
>>>>> Has anyone observed similar issues? haven't anyone used timer for PWM?
>>>>>
>>>>> Any help........Thanks in advance.
>>>>>
>>>>> Mike.
>>>>>
>>>>> --- In m...@yahoogroups.com, "mike2forums" wrote:
>>>>>> Hello Forum members,
>>>>>>
>>>>>> I am using MSP430F2618 with a XTAL of 1MHz connected to XT1 pins. The bus clock (MCLK) is 250KHz while the aux clock (ACLK) is 1MHz. I am using ACLK to different peripherals like UART, SPI, timer etc.
>>>>>>
>>>>>> Is it possible that the timer execution will get affected as the MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK will be used to execute the instructions while ACLK will drive the peripheral.
>>>>>>
>>>>>> I observed similar while working with the timer ISRs. I am using TI-MSP430FET(PIF) to debug my code having a timer ISR and updating the TBCCR0 and TBCCR1 registers. I observed a little difference in two register values when I put breakpoint in ISR. Is the debugger playing any role for timer execution?
>>>>>>
>>>>>> I have read the datasheet where it is stated that some cpu cycles will be used to enter and exit the timer ISR. How is this affecting the timer counts?
>>>>>>
>>>>>> Anyone having similar issues/observations.........?? Thanks in advance.
>>>>>>
>>>>>> Mike
>>>>>>
>>>
>>>
>>>
>>> ------------------------------------
>>>
>>>
>>>
>>>
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
the MCLK is slower than the ACLK, and I also believe it only affects the
timers, but it has been very long time since I looked and it seems to
be one of those things that has drifted out of the data sheets over time.
Not 100% sure, just have strong recollections of seeing some notes on it
many years ago.
Al
mike2forums wrote:
> Hi OneStone,
>
> It is applicable if the timer clock is asynchronous to CPU clock..similar to SCS bit, is there any option available?
>
> Mike.
> --- In m...@yahoogroups.com, OneStone
>> Mike this is mentioned in the data sheets, in fact in the user guides.
>> It is given as a warning against potential timer misreads when user an
>> MCLK that is slower than the timer clock. In SLAU144E for example this
>> is a note in para 12.2.1. There used to be a better explanation in
>> earlier manuals, but this seems to be all you get now.
>>
>> Al
>>
>> mike2forums wrote:
>>> What is the reason then? TI does not mention anything about this in datasheet. What is the solution for this?
>>>
>>> Any help.........Thanks in advance.
>>>
>>> Mike.
>>>
>>> --- In m...@yahoogroups.com, "old_cow_yellow"
>>>> Yes, I observed the same issue no matter what CPU I use. They all take one or more cycles to do anything.
>>>>
>>>> --- In m...@yahoogroups.com, "mike2forums"
>>>>> Hello members,
>>>>>
>>>>> Has anyone observed similar issues? haven't anyone used timer for PWM?
>>>>>
>>>>> Any help........Thanks in advance.
>>>>>
>>>>> Mike.
>>>>>
>>>>> --- In m...@yahoogroups.com, "mike2forums"
>>>>>> Hello Forum members,
>>>>>>
>>>>>> I am using MSP430F2618 with a XTAL of 1MHz connected to XT1 pins. The bus clock (MCLK) is 250KHz while the aux clock (ACLK) is 1MHz. I am using ACLK to different peripherals like UART, SPI, timer etc.
>>>>>>
>>>>>> Is it possible that the timer execution will get affected as the MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK will be used to execute the instructions while ACLK will drive the peripheral.
>>>>>>
>>>>>> I observed similar while working with the timer ISRs. I am using TI-MSP430FET(PIF) to debug my code having a timer ISR and updating the TBCCR0 and TBCCR1 registers. I observed a little difference in two register values when I put breakpoint in ISR. Is the debugger playing any role for timer execution?
>>>>>>
>>>>>> I have read the datasheet where it is stated that some cpu cycles will be used to enter and exit the timer ISR. How is this affecting the timer counts?
>>>>>>
>>>>>> Anyone having similar issues/observations.........?? Thanks in advance.
>>>>>>
>>>>>> Mike
>>>>>>
>>>
>>>
>>>
>>> ------------------------------------
>>>
>>>
>>>
>>>
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
RE: Re: XTAL - the oscillator - "Scott, Neil R" - Nov 25 0:37:40 2009
I liked this one because it describes different aspects of hardware. Not only are they
helping "Mike" out but also really explaining to everyone else how everything works. I
also find these types of ones interesting because it describes the specifications a little
bit more than what I have found on my own.
Neil
________________________________
From: m...@yahoogroups.com [m...@yahoogroups.com] on behalf of Michael [m...@axys.cl]
Sent: Monday, November 23, 2009 9:53 AM
To: m...@yahoogroups.com
Subject: [msp430] Re: XTAL - the oscillator
Mike,
Regardless of where the discussion has evolved to, let me say this:
> Is it possible that the timer execution will get affected as the
> MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK
> will be used to execute the instructions while ACLK will drive the
> peripheral.
You can even stop MCLK (by entering LPM for example) and the timer will continue to work.
> I observed similar while working with the timer ISRs. I am using
> TI-MSP430FET(PIF) to debug my code having a timer ISR and updating
> the TBCCR0 and TBCCR1 registers. I observed a little difference in
> two register values when I put breakpoint in ISR. Is the debugger
> playing any role for timer execution?
You are way too vague on this. I can think of a number of different interpretations of what you wrote, each with a different explanation so you will need to be much more precise when explaining what you did and what you found/what your results were.
> I have read the datasheet where it is stated that some cpu cycles
> will be used to enter and exit the timer ISR. How is this affecting
> the timer counts?
It won't affect the timer count, but it might/will affect your program flow. I don't know what you are trying to do with your timer or in the ISR, so there is nothing more to tell.
This might not relate to your problem, but I can tell you I've used a timer INCLK to measure a frequency signal of up to 80MHz using the internal 1:8 prescaller. The MSP showed the same frequency as a frequency counter connected in parallel to the same signal (taking ppm accuracy into account).
Regards,
Michael K.
--- In m...@yahoogroups.com, "mike2forums"
wrote:
>
> Hello Forum members,
>
> I am using MSP430F2618 with a XTAL of 1MHz connected to XT1 pins. The bus clock (MCLK) is 250KHz while the aux clock (ACLK) is 1MHz. I am using ACLK to different peripherals like UART, SPI, timer etc.
>
> Is it possible that the timer execution will get affected as the MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK will be used to execute the instructions while ACLK will drive the peripheral.
>
> I observed similar while working with the timer ISRs. I am using TI-MSP430FET(PIF) to debug my code having a timer ISR and updating the TBCCR0 and TBCCR1 registers. I observed a little difference in two register values when I put breakpoint in ISR. Is the debugger playing any role for timer execution?
>
> I have read the datasheet where it is stated that some cpu cycles will be used to enter and exit the timer ISR. How is this affecting the timer counts?
>
> Anyone having similar issues/observations.........?? Thanks in advance.
>
> Mike
>
[Non-text portions of this message have been removed]
------------------------------------
(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )
Neil
________________________________
From: m...@yahoogroups.com [m...@yahoogroups.com] on behalf of Michael [m...@axys.cl]
Sent: Monday, November 23, 2009 9:53 AM
To: m...@yahoogroups.com
Subject: [msp430] Re: XTAL - the oscillator
Mike,
Regardless of where the discussion has evolved to, let me say this:
> Is it possible that the timer execution will get affected as the
> MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK
> will be used to execute the instructions while ACLK will drive the
> peripheral.
You can even stop MCLK (by entering LPM for example) and the timer will continue to work.
> I observed similar while working with the timer ISRs. I am using
> TI-MSP430FET(PIF) to debug my code having a timer ISR and updating
> the TBCCR0 and TBCCR1 registers. I observed a little difference in
> two register values when I put breakpoint in ISR. Is the debugger
> playing any role for timer execution?
You are way too vague on this. I can think of a number of different interpretations of what you wrote, each with a different explanation so you will need to be much more precise when explaining what you did and what you found/what your results were.
> I have read the datasheet where it is stated that some cpu cycles
> will be used to enter and exit the timer ISR. How is this affecting
> the timer counts?
It won't affect the timer count, but it might/will affect your program flow. I don't know what you are trying to do with your timer or in the ISR, so there is nothing more to tell.
This might not relate to your problem, but I can tell you I've used a timer INCLK to measure a frequency signal of up to 80MHz using the internal 1:8 prescaller. The MSP showed the same frequency as a frequency counter connected in parallel to the same signal (taking ppm accuracy into account).
Regards,
Michael K.
--- In m...@yahoogroups.com
>
> Hello Forum members,
>
> I am using MSP430F2618 with a XTAL of 1MHz connected to XT1 pins. The bus clock (MCLK) is 250KHz while the aux clock (ACLK) is 1MHz. I am using ACLK to different peripherals like UART, SPI, timer etc.
>
> Is it possible that the timer execution will get affected as the MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK will be used to execute the instructions while ACLK will drive the peripheral.
>
> I observed similar while working with the timer ISRs. I am using TI-MSP430FET(PIF) to debug my code having a timer ISR and updating the TBCCR0 and TBCCR1 registers. I observed a little difference in two register values when I put breakpoint in ISR. Is the debugger playing any role for timer execution?
>
> I have read the datasheet where it is stated that some cpu cycles will be used to enter and exit the timer ISR. How is this affecting the timer counts?
>
> Anyone having similar issues/observations.........?? Thanks in advance.
>
> Mike
>
[Non-text portions of this message have been removed]
------------------------------------
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