Re: [fpga-cpu] Xilinx bitgen problem | Piclist

A discussion group for the PICMicro microcontroller. Also called the Microchip PIC, this list is dedicated to the use and abuse of this fine, simple, microcontroller. Close to topic posts are welcome, ie. general electronics.

Hi! Maybe what I'm going to said is stupid, but "the clk has no source".... What clk is that??? Are you using the fpga external clock??? If you are not, I think you my try it, by using pin 13. That's what I think... sorry if it's dumb... hehe ;P Thanks for listening... Jorge, Guilherme ----- Original Message ----- From: "Bharath Kumar" <bharath.kumar@w...> To: <f...@egroups.com> Sent: Thursday, January 04, 2001 6:58 AM Subject: [fpga-cpu] Xilinx bitgen problem > hi All, > I tried my first design using design manager yesterday... > I was able to succesfully complete the flow upto Place and Route(PAR).... but > "Bitgen" is giving some problem as follows: > **************************************************************************** ********* > Running DRC > ERROR:DesignRules:368 - Netcheck: Sourceless. Net clk has no source. > ERROR:DesignRules:10 - Netcheck: The signal "clk" is completely unrouted. > **************************************************************************** ************* > > I couldnt get the exact meaning of the above message...Please help me. > > thanks and Regards, > Bharath > Bangalore, INDIA > > > [Non-text portions of this message have been removed] > To Post a message, send it to: f...@eGroups.com > To Unsubscribe, send a blank message to: f...@eGroups.com

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Re: [fpga-cpu] Xilinx bitgen problem - Guil...@h... - Jan 4 20:04:00 2001