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Discussion Groups | Piclist | Re: [fpga-cpu] Xilinx bitgen problem
A discussion group for the PICMicro microcontroller. Also called the Microchip PIC, this list is dedicated to the use and abuse of this fine, simple, microcontroller. Close to topic posts are welcome, ie. general electronics.
Re: [fpga-cpu] Xilinx bitgen problem - Guil...@h... - Jan 4 20:04:00 2001
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Hi! Maybe what I'm going to said is stupid, but "the clk has no source".... What clk is that??? Are you using the fpga external clock??? If you are not, I think you my try it, by using pin 13. That's what I think... sorry if it's dumb... hehe ;P Thanks for listening... Jorge, Guilherme ----- Original Message ----- From: "Bharath Kumar" <bharath.kumar@w...> To: <f...@egroups.com> Sent: Thursday, January 04, 2001 6:58 AM Subject: [fpga-cpu] Xilinx bitgen problem > hi All, > I tried my first design using design manager yesterday... > I was able to succesfully complete the flow upto Place and Route(PAR).... but > "Bitgen" is giving some problem as follows: > **************************************************************************** ********* > Running DRC > ERROR:DesignRules:368 - Netcheck: Sourceless. Net clk has no source. > ERROR:DesignRules:10 - Netcheck: The signal "clk" is completely unrouted. > **************************************************************************** ************* > > I couldnt get the exact meaning of the above message...Please help me. > > thanks and Regards, > Bharath > Bangalore, INDIA > > > [Non-text portions of this message have been removed] > To Post a message, send it to: f...@eGroups.com > To Unsubscribe, send a blank message to: f...@eGroups.com |
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Re: [fpga-cpu] Xilinx bitgen problem - Guil...@h... - Jan 4 20:04:00 2001
|
Hi! Maybe what I'm going to said is stupid, but "the clk has no source".... What clk is that??? Are you using the fpga external clock??? If you are not, I think you my try it, by using pin 13. That's what I think... sorry if it's dumb... hehe ;P Thanks for listening... Jorge, Guilherme ----- Original Message ----- From: "Bharath Kumar" <bharath.kumar@w...> To: <f...@egroups.com> Sent: Thursday, January 04, 2001 6:58 AM Subject: [fpga-cpu] Xilinx bitgen problem > hi All, > I tried my first design using design manager yesterday... > I was able to succesfully complete the flow upto Place and Route(PAR).... but > "Bitgen" is giving some problem as follows: > **************************************************************************** ********* > Running DRC > ERROR:DesignRules:368 - Netcheck: Sourceless. Net clk has no source. > ERROR:DesignRules:10 - Netcheck: The signal "clk" is completely unrouted. > **************************************************************************** ************* > > I couldnt get the exact meaning of the above message...Please help me. > > thanks and Regards, > Bharath > Bangalore, INDIA > > > [Non-text portions of this message have been removed] > To Post a message, send it to: f...@eGroups.com > To Unsubscribe, send a blank message to: f...@eGroups.com |
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Re: Re: R/C Receiver Interface - Malcolm - Jan 28 15:19:00 2005
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Not really sure what the original requirement is as I've just joined this group, but if it's to connect a PIC to a receiver so you can get the PIC to perform a function on receipt of a signal from the transmitter (like the speed of a motor or turn on some light) then there are loads of CCts and code available on the web. If on the other hand the object is to read the PPM signals from the transmitter for use as a flight sim interface, then again there are lots of examples of how to do this on several web sites (including my own electronics site www.rc-electronics.net ) My experience is that each channel signal is a pulse with a width of between 1ms and 2.0ms, with 1.5ms being the centre point on the servo travel. Thus with a 6 channel TX you have a train of six pulses between 1 and 2 ms with a sync puls at the end of the frame. (at least this is the case with Futaba and JR transmitters). These pulses are repeated in a 20ms time frame. With this sort of timing you can use the internal oscillator in most PICs if you want to read the signals in a project such as an RC switch. However if you are interfacing with a PC you need the precision of an external crystal or resonator to maintain the data stream to the PC Regards Malcolm Michael Shiloh wrote: > It's my understanding that this is not a standard. Some transmitters > overlap a bit, e.g. an 8 channel transmitter might transmit at the > same time channels 1 and 5, 2 and 6, 3 and 7, and 4 and 8. > > Another variation is when a pulse will start; sometimes channel 2 will > go high at the same time that channel 1 goes low; in other transmitters, > channel 2 may go high 2 msec after channel 1 goes high, regardless of > how long the channel 1 pulse lasted. > > I've always written my decoders so that each channel is decoded > independently. This also allows changing channels by moving connectors, > without having to worry about whether that confuses the decoding > algorithm. I've had to do this moments before a performance ( I do > controllers for large scale R/C machine performances) and been pleased > that I didn't have to reprogram anything. > > Michael > On Fri, 28 Jan 2005 wrote: > > > > > In a message dated 1/28/2005 12:45:56 PM Eastern Standard Time, > > writes: > > > > Also, it somewhat depends on how the RC pulses come in. Do they all > > start at the same time or are they staggered? > > > > > > > > > > > > They come in as a pulse train. The PIC only has to decode one > channel at a > > time. PIC's work very nicely for decoding R/C. > > > > Randy > > _www.soaringcircuits.com_ (http://www.soaringcircuits.com) > <http://www.soaringcircuits.com%29> > > > > to unsubscribe, go to http://www.yahoogroups.com and follow the > instructions > ------------------------------------------------------------------------ > *>. |
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