Sign in
Search piclist
Subscribe to piclist
piclist by Keywords
12F675 | 16F628 | 16F84 | 16f877 | 16F877A | 16F88 | 18F458 | ADC | AVR | Bootloader | CAN | CCS | CRC | EAGLE | EEPROM | ICD | ICSP | IDE | JDM | LED | Macros | Microchip | MPLAB | PCB-CAD | PIC10F | Pic12f675 | PIC16F84 | PIC16F84A | PIC16F877 | PIC18 | PIC18F452 | PicBasic | PICC | PICSTART | PWM | RS-485 | RS232 | SMT | SPI | UART | USART | USB | Wireless | Wisp628 | Xilinx
Ads
Discussion Groups
See Also
Discussion Groups | Piclist | Re: [fpga-cpu] Xilinx bitgen problem
A discussion group for the PICMicro microcontroller. Also called the Microchip PIC, this list is dedicated to the use and abuse of this fine, simple, microcontroller. Close to topic posts are welcome, ie. general electronics.
Re: [fpga-cpu] Xilinx bitgen problem - Guil...@h... - Jan 4 20:04:00 2001
|
Hi! Maybe what I'm going to said is stupid, but "the clk has no source".... What clk is that??? Are you using the fpga external clock??? If you are not, I think you my try it, by using pin 13. That's what I think... sorry if it's dumb... hehe ;P Thanks for listening... Jorge, Guilherme ----- Original Message ----- From: "Bharath Kumar" <bharath.kumar@w...> To: <f...@egroups.com> Sent: Thursday, January 04, 2001 6:58 AM Subject: [fpga-cpu] Xilinx bitgen problem > hi All, > I tried my first design using design manager yesterday... > I was able to succesfully complete the flow upto Place and Route(PAR).... but > "Bitgen" is giving some problem as follows: > **************************************************************************** ********* > Running DRC > ERROR:DesignRules:368 - Netcheck: Sourceless. Net clk has no source. > ERROR:DesignRules:10 - Netcheck: The signal "clk" is completely unrouted. > **************************************************************************** ************* > > I couldnt get the exact meaning of the above message...Please help me. > > thanks and Regards, > Bharath > Bangalore, INDIA > > > [Non-text portions of this message have been removed] > To Post a message, send it to: f...@eGroups.com > To Unsubscribe, send a blank message to: f...@eGroups.com |
Stellaris® MCU Family: New Parts, New Package, New Price.
(You need to be a member of piclist -- send a blank email to piclist-subscribe@yahoogroups.com )
Re: [fpga-cpu] Xilinx bitgen problem - Guil...@h... - Jan 4 20:04:00 2001
|
Hi! Maybe what I'm going to said is stupid, but "the clk has no source".... What clk is that??? Are you using the fpga external clock??? If you are not, I think you my try it, by using pin 13. That's what I think... sorry if it's dumb... hehe ;P Thanks for listening... Jorge, Guilherme ----- Original Message ----- From: "Bharath Kumar" <bharath.kumar@w...> To: <f...@egroups.com> Sent: Thursday, January 04, 2001 6:58 AM Subject: [fpga-cpu] Xilinx bitgen problem > hi All, > I tried my first design using design manager yesterday... > I was able to succesfully complete the flow upto Place and Route(PAR).... but > "Bitgen" is giving some problem as follows: > **************************************************************************** ********* > Running DRC > ERROR:DesignRules:368 - Netcheck: Sourceless. Net clk has no source. > ERROR:DesignRules:10 - Netcheck: The signal "clk" is completely unrouted. > **************************************************************************** ************* > > I couldnt get the exact meaning of the above message...Please help me. > > thanks and Regards, > Bharath > Bangalore, INDIA > > > [Non-text portions of this message have been removed] > To Post a message, send it to: f...@eGroups.com > To Unsubscribe, send a blank message to: f...@eGroups.com |
(You need to be a member of piclist -- send a blank email to piclist-subscribe@yahoogroups.com )
Re: [fpga-cpu] Xilinx bitgen problem - Guil...@h... - Jan 4 20:04:00 2001
|
Hi! Maybe what I'm going to said is stupid, but "the clk has no source".... What clk is that??? Are you using the fpga external clock??? If you are not, I think you my try it, by using pin 13. That's what I think... sorry if it's dumb... hehe ;P Thanks for listening... Jorge, Guilherme ----- Original Message ----- From: "Bharath Kumar" <bharath.kumar@w...> To: <f...@egroups.com> Sent: Thursday, January 04, 2001 6:58 AM Subject: [fpga-cpu] Xilinx bitgen problem > hi All, > I tried my first design using design manager yesterday... > I was able to succesfully complete the flow upto Place and Route(PAR).... but > "Bitgen" is giving some problem as follows: > **************************************************************************** ********* > Running DRC > ERROR:DesignRules:368 - Netcheck: Sourceless. Net clk has no source. > ERROR:DesignRules:10 - Netcheck: The signal "clk" is completely unrouted. > **************************************************************************** ************* > > I couldnt get the exact meaning of the above message...Please help me. > > thanks and Regards, > Bharath > Bangalore, INDIA > > > [Non-text portions of this message have been removed] > To Post a message, send it to: f...@eGroups.com > To Unsubscribe, send a blank message to: f...@eGroups.com |
(You need to be a member of piclist -- send a blank email to piclist-subscribe@yahoogroups.com )
Re: [fpga-cpu] Xilinx bitgen problem - Guil...@h... - Jan 4 20:04:00 2001
|
Hi! Maybe what I'm going to said is stupid, but "the clk has no source".... What clk is that??? Are you using the fpga external clock??? If you are not, I think you my try it, by using pin 13. That's what I think... sorry if it's dumb... hehe ;P Thanks for listening... Jorge, Guilherme ----- Original Message ----- From: "Bharath Kumar" <bharath.kumar@w...> To: <f...@egroups.com> Sent: Thursday, January 04, 2001 6:58 AM Subject: [fpga-cpu] Xilinx bitgen problem > hi All, > I tried my first design using design manager yesterday... > I was able to succesfully complete the flow upto Place and Route(PAR).... but > "Bitgen" is giving some problem as follows: > **************************************************************************** ********* > Running DRC > ERROR:DesignRules:368 - Netcheck: Sourceless. Net clk has no source. > ERROR:DesignRules:10 - Netcheck: The signal "clk" is completely unrouted. > **************************************************************************** ************* > > I couldnt get the exact meaning of the above message...Please help me. > > thanks and Regards, > Bharath > Bangalore, INDIA > > > [Non-text portions of this message have been removed] > To Post a message, send it to: f...@eGroups.com > To Unsubscribe, send a blank message to: f...@eGroups.com |
(You need to be a member of piclist -- send a blank email to piclist-subscribe@yahoogroups.com )
Re: 16F819 Question - rtstofer - Jan 30 3:25:00 2005
|
--- In , "meriachee" <meriachee@y...> wrote: > > Thank you. What if you are using the pin for something else though? > > Pardon me, but I came to this from using Oopic where you didn't need > anything else... That's where the 'almost' comes in. There are chips where the MCLR line can be used for IO, in which case, there is no external MCLR function. But, if the pin is used for input, it must still be terminated properly. So, read the datasheet and follow the instructions. They're pretty clear about how to handle this. And it isn't true that the OOPic world doesn't concern itself with this. The same rules apply - don't allow input signals to float. > --- In , "rtstofer" <rstofer@p...> wrote: > > > > > > Almost always... Just assume it does. > > > > --- In , "meriachee" <meriachee@y...> wrote: > > > > > > That should, of course, be 16f818. > > > > > > > > > --- In , "meriachee" <meriachee@y...> > wrote: > > > > > > > > Hello, > > > > > > > > I'm using the internal osc from the PicProgrammer site, > > > > > > > > The Code Fix: > > > > PicBasic Compiler: > > > > Symbol OSCCON = $8F > > > > Poke OSCCON, $60 > > > > > > > > and the code is the first attempt at making this chip go: > > > > > > > > > > > > loop: High 0 'Turn on LED connected to RB0 > > > > Pause 500 'Delay for .5 seconds > > > > > > > > Low 0 'Turn off LED connected to RB0 > > > > Pause 500 'Delay for .5 seconds > > > > > > > > Goto loop 'Go back to loop and blink LED forever > > > > End > > > > > > > > > > > > Of course the chip does not run. > > > > > > > > Does it need a 4k7 on the mclr line to +5? > > > > > > > > Gary |
|
|
(You need to be a member of piclist -- send a blank email to piclist-subscribe@yahoogroups.com )
Can't erase 16F877 - sandeep c p - Feb 1 10:25:00 2005
|
hi i hav a used 16F877. when i try to read after erase it show "Device is data protected! Data memory may be invalid. Device is code protected! Program memory may be invalid" is this is the progblem of my PIC? i had try the 10k on RB3/PGM on the 36th pin and Gnd. still have the same message what should i do thanks __________________________________ |
Stellaris® MCU Family: New Parts, New Package, New Price.
(You need to be a member of piclist -- send a blank email to piclist-subscribe@yahoogroups.com )
Re: Can't erase 16F877 - Author Unknown - Feb 1 14:11:00 2005
|
you can try useing high volt programming mode to turn off "Code Protect" in
the configuration byte. Quoting sandeep c p <>: > hi > i hav a used 16F877. > when i try to read after erase it show > "Device is data protected! Data memory may be > invalid. > > Device is code protected! Program memory may be > invalid" > is this is the progblem of my PIC? > i had try the 10k on RB3/PGM on the 36th pin and Gnd. > still have the same message > > what should i do > thanks > > __________________________________ > to unsubscribe, go to http://www.yahoogroups.com and follow the > instructions > Yahoo! Groups Links |
Stellaris® MCU Family: New Parts, New Package, New Price.
(You need to be a member of piclist -- send a blank email to piclist-subscribe@yahoogroups.com )
Re: Can't erase 16F877 - sandeep c p - Feb 1 21:46:00 2005
|
i try the HV mode.still have the same problem. thanks __________________________________ |
(You need to be a member of piclist -- send a blank email to piclist-subscribe@yahoogroups.com )