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Discussion Groups | Rabbit-Semi | Maximum SPI clock rate for RCM3400
This is a group for folks designing and programming embedded systems using the Rabbit Semiconductor C-programmable microcontroller. Rabbit Semi is a spin-off from Z-World who makes a variety of embedded modules and tools. This group is not affiliated with either Rabbit or Z-World, but is a user forum for sharing ideas, asking questions, flaunting knowledge, and other typical user group stuff. The Rabbit is a powerful uC, supported by a full-featured C-compiler.
Maximum SPI clock rate for RCM3400 - jpotter2 - Mar 3 8:20:17 2008
I need to generate an SPI data stream with a clock rate of at least 6
MHz. Ultimately I would like to go to 30 MHz if anyone has suggestions
about how to do that. I need to send a command string to an Analog
Devices DDS chip so I can change the phase of a pair of channels in an
arbitrary way. The data stream would be about 480 clock cycles at 6
MHz. If I can manage 30 MHz I would need about 2400 clock cycles,
counting the delay between bytes/words.
I am using an RCM3400 on the corresponding prototype board. I am stuck
with that for the moment. The SPI library routines suggests limiting
the CLK_RATE_DIVISOR to 5 or more. The divisor is applied to something
called perclk. I can't find the definition of that anywhere in the
literature on the 3000 series chip or the core module.
As I understand it, the RCM3400 has a system clock of 29.4 MHz which
is derived by doubling from a 14.7 MHz oscillator. If the limit on the
CLK_RATE_DIVISOR is 5 and the limit means I can achieve 29.4/5 I may
be OK. That comes to 5.88 MHz which is close enough for now.
I have been looking for a memory device that I could program with my
data and dump at higher clock frequencies. The Atmel SLD devices look
promising but they share the output pins with some of the address
lines which makes things a little tricky.
The data stream consists of an 8 bit byte followed by a 16 bit word.
After the 16 bit word I need to generate an IOSTROBE. This sequence
needs to repeat for 80 usec at whatever clock rate I can achieve. A 6
MHz clock lets me send 16 sequences and a 30 MHz clock lets me send 80
sequences. Thus I can update the output phase every 5 usec in the
former case and every one usec in the latter.
I need to be able to occasionally reprogram the 16 bit word, but I
don't expect to do it often. Perhaps once a day.
I am hardware oriented and have some experience with the RCM3400
controlling the AD9959 DDS chip, but I am not fully up to date on all
the whiz bang chips available these days. I have thought of using a
fast DSP chip to both read the phase error and generate the correction
but I don't have any DSP experience yet and I'd like to get this
project off the ground reasonably simply.
Any clarification of the maximum achievable SPI clock rate for the
RCM3400 would be greatly appreciated as well as any suggestions about
how to generate the faster data stream under control of the
microprocessor.
Thanks,
Jim
(You need to be a member of rabbit-semi -- send a blank email to rabbit-semi-subscribe@yahoogroups.com )
MHz. Ultimately I would like to go to 30 MHz if anyone has suggestions
about how to do that. I need to send a command string to an Analog
Devices DDS chip so I can change the phase of a pair of channels in an
arbitrary way. The data stream would be about 480 clock cycles at 6
MHz. If I can manage 30 MHz I would need about 2400 clock cycles,
counting the delay between bytes/words.
I am using an RCM3400 on the corresponding prototype board. I am stuck
with that for the moment. The SPI library routines suggests limiting
the CLK_RATE_DIVISOR to 5 or more. The divisor is applied to something
called perclk. I can't find the definition of that anywhere in the
literature on the 3000 series chip or the core module.
As I understand it, the RCM3400 has a system clock of 29.4 MHz which
is derived by doubling from a 14.7 MHz oscillator. If the limit on the
CLK_RATE_DIVISOR is 5 and the limit means I can achieve 29.4/5 I may
be OK. That comes to 5.88 MHz which is close enough for now.
I have been looking for a memory device that I could program with my
data and dump at higher clock frequencies. The Atmel SLD devices look
promising but they share the output pins with some of the address
lines which makes things a little tricky.
The data stream consists of an 8 bit byte followed by a 16 bit word.
After the 16 bit word I need to generate an IOSTROBE. This sequence
needs to repeat for 80 usec at whatever clock rate I can achieve. A 6
MHz clock lets me send 16 sequences and a 30 MHz clock lets me send 80
sequences. Thus I can update the output phase every 5 usec in the
former case and every one usec in the latter.
I need to be able to occasionally reprogram the 16 bit word, but I
don't expect to do it often. Perhaps once a day.
I am hardware oriented and have some experience with the RCM3400
controlling the AD9959 DDS chip, but I am not fully up to date on all
the whiz bang chips available these days. I have thought of using a
fast DSP chip to both read the phase error and generate the correction
but I don't have any DSP experience yet and I'd like to get this
project off the ground reasonably simply.
Any clarification of the maximum achievable SPI clock rate for the
RCM3400 would be greatly appreciated as well as any suggestions about
how to generate the faster data stream under control of the
microprocessor.
Thanks,
Jim
(You need to be a member of rabbit-semi -- send a blank email to rabbit-semi-subscribe@yahoogroups.com )
Re: Maximum SPI clock rate for RCM3400 - neil2452 - Mar 3 11:51:54 2008
I am currently working on a driver for a 32Mhz SPI type interface to
a string of MAXIM6974 devices. I came to the conclusion that using
any uP to do a "bit bang" was never going to come close to my
required speed. I am now taking the approach of using a either a
FPGA or CPLD to do the interface. Since I have no experience of
these I am just getting to grips with learning to use the ISEWeb
tools from Xilinx and one of there CPLD dev kits.
>From my progress so far I believe I will be able to do it with
xc2c256 Xlinkx CPLD. The CPLD's seem a bit easier to use than an
FPGA as all the configuration fuse are on the chip itself. The
FPGA's seem to need another memory chip to hold the config in. More
complication.
To build my driver interface I am going to use a 64K-128K dual port
memory. The first bus will be to the uP address and data bus. The
other port will be connected to the CPLD. Thus uP will put the
required data in the memory and then send a signal to the CPLD to
tell it to send it at the required 32Mhz bit rate. The CPLD will
read an data length from the memory and then serilise each succesive
byte from memroy up to the required count.
This way the uP is free to work out the next set of data to send
while the CPLD is sending the first set. Essentially I am building a
memory mapped display interface.
I would do some research on using a CPLD/FPGAs, they can do parellel
logic at blistering speeds, 50-100Mhz would probably not be
imposible. Any sequential uP approach I think would struggle to
above a few Mhz.
Neil
--- In r...@yahoogroups.com, "jpotter2" wrote:
>
> I need to generate an SPI data stream with a clock rate of at least
6
> MHz. Ultimately I would like to go to 30 MHz if anyone has
suggestions
> about how to do that. I need to send a command string to an Analog
> Devices DDS chip so I can change the phase of a pair of channels in
an
> arbitrary way. The data stream would be about 480 clock cycles at 6
> MHz. If I can manage 30 MHz I would need about 2400 clock cycles,
> counting the delay between bytes/words.
>
> I am using an RCM3400 on the corresponding prototype board. I am
stuck
> with that for the moment. The SPI library routines suggests limiting
> the CLK_RATE_DIVISOR to 5 or more. The divisor is applied to
something
> called perclk. I can't find the definition of that anywhere in the
> literature on the 3000 series chip or the core module.
>
> As I understand it, the RCM3400 has a system clock of 29.4 MHz which
> is derived by doubling from a 14.7 MHz oscillator. If the limit on
the
> CLK_RATE_DIVISOR is 5 and the limit means I can achieve 29.4/5 I may
> be OK. That comes to 5.88 MHz which is close enough for now.
>
> I have been looking for a memory device that I could program with my
> data and dump at higher clock frequencies. The Atmel SLD devices
look
> promising but they share the output pins with some of the address
> lines which makes things a little tricky.
>
> The data stream consists of an 8 bit byte followed by a 16 bit word.
> After the 16 bit word I need to generate an IOSTROBE. This sequence
> needs to repeat for 80 usec at whatever clock rate I can achieve. A
6
> MHz clock lets me send 16 sequences and a 30 MHz clock lets me send
80
> sequences. Thus I can update the output phase every 5 usec in the
> former case and every one usec in the latter.
>
> I need to be able to occasionally reprogram the 16 bit word, but I
> don't expect to do it often. Perhaps once a day.
>
> I am hardware oriented and have some experience with the RCM3400
> controlling the AD9959 DDS chip, but I am not fully up to date on
all
> the whiz bang chips available these days. I have thought of using a
> fast DSP chip to both read the phase error and generate the
correction
> but I don't have any DSP experience yet and I'd like to get this
> project off the ground reasonably simply.
>
> Any clarification of the maximum achievable SPI clock rate for the
> RCM3400 would be greatly appreciated as well as any suggestions
about
> how to generate the faster data stream under control of the
> microprocessor.
>
> Thanks,
>
> Jim
>
(You need to be a member of rabbit-semi -- send a blank email to rabbit-semi-subscribe@yahoogroups.com )
a string of MAXIM6974 devices. I came to the conclusion that using
any uP to do a "bit bang" was never going to come close to my
required speed. I am now taking the approach of using a either a
FPGA or CPLD to do the interface. Since I have no experience of
these I am just getting to grips with learning to use the ISEWeb
tools from Xilinx and one of there CPLD dev kits.
>From my progress so far I believe I will be able to do it with
xc2c256 Xlinkx CPLD. The CPLD's seem a bit easier to use than an
FPGA as all the configuration fuse are on the chip itself. The
FPGA's seem to need another memory chip to hold the config in. More
complication.
To build my driver interface I am going to use a 64K-128K dual port
memory. The first bus will be to the uP address and data bus. The
other port will be connected to the CPLD. Thus uP will put the
required data in the memory and then send a signal to the CPLD to
tell it to send it at the required 32Mhz bit rate. The CPLD will
read an data length from the memory and then serilise each succesive
byte from memroy up to the required count.
This way the uP is free to work out the next set of data to send
while the CPLD is sending the first set. Essentially I am building a
memory mapped display interface.
I would do some research on using a CPLD/FPGAs, they can do parellel
logic at blistering speeds, 50-100Mhz would probably not be
imposible. Any sequential uP approach I think would struggle to
above a few Mhz.
Neil
--- In r...@yahoogroups.com, "jpotter2"
>
> I need to generate an SPI data stream with a clock rate of at least
6
> MHz. Ultimately I would like to go to 30 MHz if anyone has
suggestions
> about how to do that. I need to send a command string to an Analog
> Devices DDS chip so I can change the phase of a pair of channels in
an
> arbitrary way. The data stream would be about 480 clock cycles at 6
> MHz. If I can manage 30 MHz I would need about 2400 clock cycles,
> counting the delay between bytes/words.
>
> I am using an RCM3400 on the corresponding prototype board. I am
stuck
> with that for the moment. The SPI library routines suggests limiting
> the CLK_RATE_DIVISOR to 5 or more. The divisor is applied to
something
> called perclk. I can't find the definition of that anywhere in the
> literature on the 3000 series chip or the core module.
>
> As I understand it, the RCM3400 has a system clock of 29.4 MHz which
> is derived by doubling from a 14.7 MHz oscillator. If the limit on
the
> CLK_RATE_DIVISOR is 5 and the limit means I can achieve 29.4/5 I may
> be OK. That comes to 5.88 MHz which is close enough for now.
>
> I have been looking for a memory device that I could program with my
> data and dump at higher clock frequencies. The Atmel SLD devices
look
> promising but they share the output pins with some of the address
> lines which makes things a little tricky.
>
> The data stream consists of an 8 bit byte followed by a 16 bit word.
> After the 16 bit word I need to generate an IOSTROBE. This sequence
> needs to repeat for 80 usec at whatever clock rate I can achieve. A
6
> MHz clock lets me send 16 sequences and a 30 MHz clock lets me send
80
> sequences. Thus I can update the output phase every 5 usec in the
> former case and every one usec in the latter.
>
> I need to be able to occasionally reprogram the 16 bit word, but I
> don't expect to do it often. Perhaps once a day.
>
> I am hardware oriented and have some experience with the RCM3400
> controlling the AD9959 DDS chip, but I am not fully up to date on
all
> the whiz bang chips available these days. I have thought of using a
> fast DSP chip to both read the phase error and generate the
correction
> but I don't have any DSP experience yet and I'd like to get this
> project off the ground reasonably simply.
>
> Any clarification of the maximum achievable SPI clock rate for the
> RCM3400 would be greatly appreciated as well as any suggestions
about
> how to generate the faster data stream under control of the
> microprocessor.
>
> Thanks,
>
> Jim
>
(You need to be a member of rabbit-semi -- send a blank email to rabbit-semi-subscribe@yahoogroups.com )
Re: Re: Maximum SPI clock rate for RCM3400 - Alexis - Mar 3 15:47:43 2008
neil2452 wrote:
>
> I am currently working on a driver for a 32Mhz SPI type interface to
> a string of MAXIM6974 devices. I came to the conclusion that using
> any uP to do a "bit bang" was never going to come close to my
> required speed. I am now taking the approach of using a either a
> FPGA or CPLD to do the interface. Since I have no experience of
> these I am just getting to grips with learning to use the ISEWeb
> tools from Xilinx and one of there CPLD dev kits.
>
> >From my progress so far I believe I will be able to do it with
> xc2c256 Xlinkx CPLD. The CPLD's seem a bit easier to use than an
> FPGA as all the configuration fuse are on the chip itself. The
> FPGA's seem to need another memory chip to hold the config in. More
> complication.
>
> To build my driver interface I am going to use a 64K-128K dual port
> memory. The first bus will be to the uP address and data bus. The
> other port will be connected to the CPLD. Thus uP will put the
> required data in the memory and then send a signal to the CPLD to
> tell it to send it at the required 32Mhz bit rate. The CPLD will
> read an data length from the memory and then serilise each succesive
> byte from memroy up to the required count.
>
> This way the uP is free to work out the next set of data to send
> while the CPLD is sending the first set. Essentially I am building a
> memory mapped display interface.
>
> I would do some research on using a CPLD/FPGAs, they can do parellel
> logic at blistering speeds, 50-100Mhz would probably not be
> imposible. Any sequential uP approach I think would struggle to
> above a few Mhz.
>
> Neil
>
> --- In r...@yahoogroups.com
>, "jpotter2" wrote:
> >
> > I need to generate an SPI data stream with a clock rate of at least
> 6
> > MHz. Ultimately I would like to go to 30 MHz if anyone has
> suggestions
> > about how to do that. I need to send a command string to an Analog
> > Devices DDS chip so I can change the phase of a pair of channels in
> an
> > arbitrary way. The data stream would be about 480 clock cycles at 6
> > MHz. If I can manage 30 MHz I would need about 2400 clock cycles,
> > counting the delay between bytes/words.
> >
> > I am using an RCM3400 on the corresponding prototype board. I am
> stuck
> > with that for the moment. The SPI library routines suggests limiting
> > the CLK_RATE_DIVISOR to 5 or more. The divisor is applied to
> something
> > called perclk. I can't find the definition of that anywhere in the
> > literature on the 3000 series chip or the core module.
> >
> > As I understand it, the RCM3400 has a system clock of 29.4 MHz which
> > is derived by doubling from a 14.7 MHz oscillator. If the limit on
> the
> > CLK_RATE_DIVISOR is 5 and the limit means I can achieve 29.4/5 I may
> > be OK. That comes to 5.88 MHz which is close enough for now.
> >
> > I have been looking for a memory device that I could program with my
> > data and dump at higher clock frequencies. The Atmel SLD devices
> look
> > promising but they share the output pins with some of the address
> > lines which makes things a little tricky.
> >
> > The data stream consists of an 8 bit byte followed by a 16 bit word.
> > After the 16 bit word I need to generate an IOSTROBE. This sequence
> > needs to repeat for 80 usec at whatever clock rate I can achieve. A
> 6
> > MHz clock lets me send 16 sequences and a 30 MHz clock lets me send
> 80
> > sequences. Thus I can update the output phase every 5 usec in the
> > former case and every one usec in the latter.
> >
> > I need to be able to occasionally reprogram the 16 bit word, but I
> > don't expect to do it often. Perhaps once a day.
> >
> > I am hardware oriented and have some experience with the RCM3400
> > controlling the AD9959 DDS chip, but I am not fully up to date on
> all
> > the whiz bang chips available these days. I have thought of using a
> > fast DSP chip to both read the phase error and generate the
> correction
> > but I don't have any DSP experience yet and I'd like to get this
> > project off the ground reasonably simply.
> >
> > Any clarification of the maximum achievable SPI clock rate for the
> > RCM3400 would be greatly appreciated as well as any suggestions
> about
> > how to generate the faster data stream under control of the
> > microprocessor.
> >
> > Thanks,
> >
> > Jim
> >
SPI is simply a parallel to serial to parallel converter with a
synchronous clock. One can easily achieve "blistering speeds" if you
choose a CPU quick enough. (Look at the ARM 9 range) To design the
interface onto a CPLD would also be easy. The XC9536 and XC9572 from
Xilinx would suffice. A double buffered parallel to serial system should
only take a few hours to implement and simulate.
A.
(You need to be a member of rabbit-semi -- send a blank email to rabbit-semi-subscribe@yahoogroups.com )
>
> I am currently working on a driver for a 32Mhz SPI type interface to
> a string of MAXIM6974 devices. I came to the conclusion that using
> any uP to do a "bit bang" was never going to come close to my
> required speed. I am now taking the approach of using a either a
> FPGA or CPLD to do the interface. Since I have no experience of
> these I am just getting to grips with learning to use the ISEWeb
> tools from Xilinx and one of there CPLD dev kits.
>
> >From my progress so far I believe I will be able to do it with
> xc2c256 Xlinkx CPLD. The CPLD's seem a bit easier to use than an
> FPGA as all the configuration fuse are on the chip itself. The
> FPGA's seem to need another memory chip to hold the config in. More
> complication.
>
> To build my driver interface I am going to use a 64K-128K dual port
> memory. The first bus will be to the uP address and data bus. The
> other port will be connected to the CPLD. Thus uP will put the
> required data in the memory and then send a signal to the CPLD to
> tell it to send it at the required 32Mhz bit rate. The CPLD will
> read an data length from the memory and then serilise each succesive
> byte from memroy up to the required count.
>
> This way the uP is free to work out the next set of data to send
> while the CPLD is sending the first set. Essentially I am building a
> memory mapped display interface.
>
> I would do some research on using a CPLD/FPGAs, they can do parellel
> logic at blistering speeds, 50-100Mhz would probably not be
> imposible. Any sequential uP approach I think would struggle to
> above a few Mhz.
>
> Neil
>
> --- In r...@yahoogroups.com
>
> >
> > I need to generate an SPI data stream with a clock rate of at least
> 6
> > MHz. Ultimately I would like to go to 30 MHz if anyone has
> suggestions
> > about how to do that. I need to send a command string to an Analog
> > Devices DDS chip so I can change the phase of a pair of channels in
> an
> > arbitrary way. The data stream would be about 480 clock cycles at 6
> > MHz. If I can manage 30 MHz I would need about 2400 clock cycles,
> > counting the delay between bytes/words.
> >
> > I am using an RCM3400 on the corresponding prototype board. I am
> stuck
> > with that for the moment. The SPI library routines suggests limiting
> > the CLK_RATE_DIVISOR to 5 or more. The divisor is applied to
> something
> > called perclk. I can't find the definition of that anywhere in the
> > literature on the 3000 series chip or the core module.
> >
> > As I understand it, the RCM3400 has a system clock of 29.4 MHz which
> > is derived by doubling from a 14.7 MHz oscillator. If the limit on
> the
> > CLK_RATE_DIVISOR is 5 and the limit means I can achieve 29.4/5 I may
> > be OK. That comes to 5.88 MHz which is close enough for now.
> >
> > I have been looking for a memory device that I could program with my
> > data and dump at higher clock frequencies. The Atmel SLD devices
> look
> > promising but they share the output pins with some of the address
> > lines which makes things a little tricky.
> >
> > The data stream consists of an 8 bit byte followed by a 16 bit word.
> > After the 16 bit word I need to generate an IOSTROBE. This sequence
> > needs to repeat for 80 usec at whatever clock rate I can achieve. A
> 6
> > MHz clock lets me send 16 sequences and a 30 MHz clock lets me send
> 80
> > sequences. Thus I can update the output phase every 5 usec in the
> > former case and every one usec in the latter.
> >
> > I need to be able to occasionally reprogram the 16 bit word, but I
> > don't expect to do it often. Perhaps once a day.
> >
> > I am hardware oriented and have some experience with the RCM3400
> > controlling the AD9959 DDS chip, but I am not fully up to date on
> all
> > the whiz bang chips available these days. I have thought of using a
> > fast DSP chip to both read the phase error and generate the
> correction
> > but I don't have any DSP experience yet and I'd like to get this
> > project off the ground reasonably simply.
> >
> > Any clarification of the maximum achievable SPI clock rate for the
> > RCM3400 would be greatly appreciated as well as any suggestions
> about
> > how to generate the faster data stream under control of the
> > microprocessor.
> >
> > Thanks,
> >
> > Jim
> >
SPI is simply a parallel to serial to parallel converter with a
synchronous clock. One can easily achieve "blistering speeds" if you
choose a CPU quick enough. (Look at the ARM 9 range) To design the
interface onto a CPLD would also be easy. The XC9536 and XC9572 from
Xilinx would suffice. A double buffered parallel to serial system should
only take a few hours to implement and simulate.
A.
(You need to be a member of rabbit-semi -- send a blank email to rabbit-semi-subscribe@yahoogroups.com )