Designing Embedded Systems with FPGA-2

Posted by Pragnesh Patel on Nov 13 2007 under   

In last part, we created hardware design of basic system. The next step is to generate (compile) hardware design. Compiled hardware design is known as bit-stream and stored in *.bit file. To compile hardware, use hardware->generate hardware tab. The complete hardware design generation takes several seconds to several minutes depending on computer speed and design complexity. In back ground, the whole design process involves many different steps including synthesis, placement, routing and run time checking. If we use VHDL to write and generate hardware design, we must follow all these steps in sequence, but Xilinx EDK is making life easier for embedded system by executing all these steps in sequence in background.

 

 

Compilation generates design report and stored in system.map.mrp file and displayed in output part of console window that looks like,

 

++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

 

analysis completed Tue Oct 30 20:18:40 2007

--------------------------------------------------------------------------------

 

Generating Report ...

 

Number of warnings: 0

Number of info messages: 2

Total time: 5 secs

 

 

xflow done!

*********************************************

Running Bitgen..

*********************************************

cd implementation; bitgen -w -f bitgen.ut system

 

Release 9.1.02i - Bitgen J.33

Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.

 

Loading device for application Rf_Device from file '3s500e.nph' in environment

C:\Xilinx91i.

 

"system" is an NCD, version 3.1, device xc3s500e, package fg320, speed -4

 

Opened constraints file system.pcf.

 

Tue Oct 30 20:18:43 2007

 

Running DRC.

 

DRC detected 0 errors and 0 warnings.

 

Creating bit map...

 

Saving bit stream in "system.bit".

 

Bitstream generation is complete.

 

Done!

+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

 

Once hardware design get finished, we need to generate software libraries and board support package using software->Generate Libraries and BSPs tab. (Use following screen for reference). If you look in your project folder *.mhs is hardware description file and *.mss is software description file used for generation.

 

 

and message in output window is,

 

+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

Libraries generated in D:\FPGA\BookSample1\microblaze_0\lib\ directory

 

Running execs_generate for OS'es, Drivers and Libraries ...

 

LibGen Done.

 

Done!

+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

 

The final step is to compile software for applications for testing memory and peripheral created by base system builder wizard. Use software->Build All User Applications tab to compile software applications. EDK uses GCC to compile software applications written for Microblaze.

 

If you look at Application tab in project information area (or project explorer), you will see two defaults and two projects. We will not discuss about defaults. Out of two projects, TestApp_Memory is marked green and TestApp_Peripheral is marked with cross (see following pic.)

 

 

So out of two projects TestApp_Memory is marked to go in default memory which starts from 0x0 location and will run immediately after reset of processor. Other projects share memory but not placed from 0x0. To execute such projects, software controlled execution point transfer is required. We will learn more about that later on. So be ready to get result from first basic design next time.

 

 

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posted by Pragnesh Patel
Instrumentation and control engineer with over 18 years in instrumentation and control engineering, software development and embedded systems experience. Worked on 8085, 8051, TI MSC1210, Z8 Encore, ATMEL AVR, pSOC USB controllers, ATMEL, Philips and ST ARM, Xilinx FPGA based embedded system development and products. Good hands on with industrial as well as consumer market products. Good programming experience with C and VB on PC plateform and C, Assembly and VHDL for embedded systems.

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It should work if you find a port or able to port the RTLinux kernel. I have no practical experience of porting RT-Linux for Microblaze or Altera.

does altera board work with RT-Linux

Any one is Ok. I actually worked once with uClinux and SPARTAN 3E starter kit.

Hello. ı want to ask a question.

Which one is useful for embedded linux , xilinx ML403 or ML405 development kits?

For I2C,

(1) you can implement in hardware, look at opencores.org and you will find VHDL for implementing I2C core.

(2) You can also do bitbanging in microblaze software if you wanna talk less then 100 KHz speed.

(3) I am no VHDL guru, so normally what I do is use small picoblaze to read ADCs, I2C or SPI peripheral and store them in common registers shared between picoblaze and microblaze. That way microblaze is free from bitbanging ports. Picoblaze can also implement moving average filters if required and let microblaze get smooth result.

I am working on FPGA, how to implement I2c
in fpga?. Kindly suggest.

Good evening sir,

I am a student in University Malaya, Malaysia.Your website is simply superb. I am doing a project that is using Xilinx EDK and Virtex-4(ML401). Do you have any tutorial for Ml401?
Although I am using Virtex 4 (ML401) and Xilinx EDK 9.2, the tutorial that I obtained is on Virtex4 (ML403). I just followed the tutorial, I just changed to my board specification. The problem occur is that the hyperterminal does not display any out put. I can send to you the coding to your email. May I know your email address? Can you please rectify my problem?

Please do reply to me as soon as possible. Your help is really being appreciated.
Thank you.

hi pragnesh,

i am working on arm7tdmi target board. can you suggest me how to erase and program external flash.