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VHDL
Comp.Arch.Embedded is a worldwide Usenet news group that is used to discuss various aspects of Embedded Systems development.
We found 230 threads matching "vhdl"
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The most relevant threads are listed first
Getting started VHDL, VHDL for Dummies, Easy Steps for FPGA experiments
Kutaj Vamor - 2005-09-25 05:33:00
Dear FPGA and VHDL Experts,
I am new to FPGA and VHDL. I would like to learn VHDL and start
experimenting FPGA. I beleive I learn faster and better by experimenting.
What would you recommend for beginners like me to getting started with VHDL
and FPGA experimentation ?
Which SW (for WinXP an...
Re: need help on a 8051 ip core
Joe - 2004-07-27 14:57:00
jpmcg wrote:
> Hi there folks i`m currently doing a msc project and trying to
> implement a 8051 ip core and program it using 'C'. Porblem is i cant
> find an ip core that will let me use it without having to spend money
> on it. As i am a student i cant get my hands on that kind of cash....Basic VHDL Development kit
Tom Lucas - 2007-10-02 10:39:00
Does anybody have any suggestions for a cheap and basic development kit
to practice VHDL on? It doesn't need to do much more than toggle a few
output pins and I'm happy to make up my own programming leads etc. UK
based distributors would be preferred.
...VHDL/Verilog Book Recomendations?
PagCal - 2006-01-19 05:19:00
What would be the best starter book for learning both VHDL and Verilog?
As well, the book should talk about design techniques of CPLD's and FPGA's.
...vhdl code
jebei.jabai - 2009-02-25 07:49:00
I have to generate digital PWM from UP-1 board.ALTERA UP-1 board has
internal clock where the value is 25 MHz. These clock needs to be divided
first in order to can create PWM with 40 kHz frequency and 0.75 duty
cycle.Can someone send me a VHDL CODE for a clock divider. Please show by
example, I'm n...can bus on fpga
mungam - 2006-03-09 04:27:00
Hello,
I would like to implement a can bus protocol on a fpga in a way to link
a PC and a can bus via a fpga PCI / I/O board. Does anyone has advice
or sources in vhdl to do that (I can't download the vhdl sources of the
opencores site, the link may be dead).
Thank you
Adrien
...interfacing a xilinx FPGA with a coldfire processor
dargo - 2009-01-03 09:37:00
Hi,
I'm looking for advice to implement on my FPGA (Xilinx SPARTAN 3A) a VHDL
interface with an external COLDFIRE processor. Due to hardware
considerations (not mine) I need to use 9 bits of address and 16 bits of
datas,
The following signals are available on my incoming pinout : TA, TEA, CS1,
IRQ...Re: c.hlp
2007-05-22 21:28:00
On May 22, 7:43 pm, ghel...@lycos.com wrote:
> On May 22, 8:50 am, thomas....@gmail.com wrote:
>
> > Hi,
>
> > I am new to C language programming. I wonder if there is a c.hlp
> > reference guide fro ANSI C available on the net that I can download.
>
> > Thank you.
>
>
...MIL-STD -1553 bus protocol design help
pshabnavees - 2007-01-18 08:14:00
hi
i am doing a project on MIL-STd-1553B. my project is to design and
implement the mil-std-1553B bus protocol using VHDL.
i could gather only info regarding the protocol concepts but not any
design helping topics in VHDL. i would be thankful if someone can help
me in guiding me or sugg...I2C master connected and tested with LEON Processor
Pinhas - 2007-08-10 06:04:00
This design uses the open core's I2C master. The core's CPU interface
is
modified from WISHBONE to AMBA/APB. The latter is done in order to
test the
core and its new APB interface with LEON processor. LEON is written in
VHDL
therefor the core's VHDL RTL design is tested.
The core also...Re: HC11 Transistor Architecture
2005-11-02 14:31:00
Grant Edwards wrote:
> Is RTL synthesizable, or is it just for simulation?
RTL isn't a specific language, it's a level of abstraction. I'm not
sure of a formal definition, but in general it involves defining
registers and the data paths and conbinatorial logic that links them.
RTL code wo...Cheapest FPGA board to study VHDL on
samiam - 2006-10-18 12:33:00
Figured this was the place to ask (comp.arch.embedded or comp.arch.fpga)
Whats the cheapest board to study VHDL on?
Ideally Id like an FPGA based board with a few inputs (dip
switches,toggles?), some outputs (parallel or serial connector, some
leds) < $100
I am looking on ebay now, and ...What graphical entry/documentation tools?
jamesp - 2005-12-08 11:36:00
Hi,
I am a mature student will be doing some complex VHDL and Verilog design
work for my course. As well as having to create and test the
functionality of the design (in both languages) I want to document how
the design is put together and it's complex hierarchy.
Is there anything out th...VHDL code for 16-32 bit counter for quadrature encoder signals (A-B)
2004-09-07 09:03:00
I'm new to VHDL and I want to learn as with examples.
I want to build a 16,24 or 32 bit counter for quadrature encoder signals (ie
A,B signals).
Can someone help me how to create following functionality in VHDL ?
Inputs are
(1,2) A, B = A,B quadrature signals (from encoder)
( 3) ID...VHDL and Verilog - 15 x Contract Engineers Required Urgently - Long Term Contract
Specialist Verilog Engineers Roles - 2007-06-27 09:28:00
My client is an award winning leader in their global field, and
looking to expand their broadcast engineering team. If you are an
engineer with strong Verilog VHDL experience then we would like to
hear from you. C++ and FPGA experience would be a nice to have. If you
want to be part of an unriva...Re: Found: The perfect dev board
joe4702 - 2007-10-01 11:27:00
On Sep 28, 5:48 pm, somepr...@yahoo.com wrote:
> I think I just found the motherload here....
>
> Im a computer scientist whos just beginning to get into EE as a hobby
> and have been looking for development boards for quite sometime.
Depending on what you are planning to do, you might al...2D array of std_logic_vector in VHDL
westocl - 2009-08-04 11:55:00
Hello all.
I am new to VHDL and I was looking for help crating a 2D array of
std_logic_vectors and initilizing it.
i think i got the first part correct, as there were no errors compiling
and syntesizing in ISE.
my sytax is
type ARR is array (1 downto 0, 1 downto 0) of std_logic_vector(...Re: c.hlp
2007-05-24 12:10:00
On May 22, 6:29 pm, thomas....@gmail.com wrote:
> On May 22, 7:43 pm, ghel...@lycos.com wrote:
>
> > On May 22, 8:50 am, thomas....@gmail.com wrote:
>
> > > Hi,
>
> > > I am new to C language programming. I wonder if there is a c.hlp
> > > reference guide fro ANSI C available ...USB3300 - Xilinx ML401 interface ...
zubinkumar - 2009-06-09 07:38:00
Hi,
I wanted to send some data from the USB port of my computer to the Xilinx
ML401 board via the USB3300 card. My restriction is that I cannot use the
MircoBlaze package. When I connect the USB3300 to the Xilinx board and then
to the USB port of my computer, I donot get a VID and PID. I wanted to ...Schematic Edition Tool : Suggestions
Francisco Camarero - 2004-03-16 02:10:00
Hello !
We are an academic institution teaching our students VLSI design, from FPGA
to full custom ASIC. We have put great value on teaching VHDL during the
past years with very good results from our students.
However, we have the impression that these students have difficulties
working...Re: what is system C.
Hans - 2006-10-22 04:51:00
SystemC is a concurrent (parallel) language similar to languages like VHDL
and Verilog whereas C is an untimed sequential language. SystemC doesn't
"generate" synthesisable descriptions, for that you need a SystemC synthesis
tool like Celoxica's Agility.
If you are thinking of using an FPGA...Using Spartan 3e
Manish - 2006-11-21 07:50:00
Hi everyone,
Does any one has used Sparan 3e with ise 8.02i??Please help me to learn
VHDL.If you have any tutorial then post
...can't read load memory contents
dartanian - 2007-11-23 06:19:00
Hello there, one of new members around here.
I've got a problem while i try to retrieve/pass over some values to
memory. I use EDK 9.1 and a system of microblaze, opb bus and opb bram
memory.
I try to retrieve some values from memory through a vhdl testbench,
which is port mapped in the PORT ...Simulating Microblaze Core + C Code + VHDL defined peripherical
Xabier Iturbe - 2006-11-23 03:15:00
Iam designing a system consisting of:
Microblaze Core
RS232 Uart Lite
SPI controller
The SPI controller will communicate with an ADC converter placed
outside of FPGA. In order to modelize the system, previous to implement
it, I have included an VHDL model of the converter.
I don=B4t kno...Available: Detailed RISC CPU IP Core Design Documentation
John Gulbrandsen - 2007-04-10 12:17:00
Hello,
I have put up an article on our web site that describes a RISC CPU IP Core
that was created for one of our clients:
http://www.summitsoftconsulting.com/Pic10IpCore.htm
The RISC IP Core is instruction-compatible with the Microchip
PIC10F200-series of microcontrollers. Full design docu...Re: Emulating a processor
Damiano - 2005-11-22 08:35:00
Hi Gromer
Why not to take an approach to vhdl.
Instead of emulating you can simulate and even synthesize.
If your aim is to better understand how a processor work this may give you a
deeper understanding.
Also there are numerous processor cores available as open source in vhdl,
mainly micr...Re: Deja Vu, All Over Again...
paris - 2004-04-10 04:43:00
(snip)
> A good example of why coderight (unfortunately) is not more popular
> occurred with a large Unix based company I worked for. I did what I
> always do, with short edits in vi or emacs, but I take the souce
> back to my PC for codewright on serious edits (can't beat the macros).
> I...RTL for Z8000 series CPU?
ajcrm125 - 2005-12-22 14:24:00
Hey guys, does anyone know where I can get VHDL/Verilog source for the
Z8001/Z8002 processor?
Thanks for any info!
-Adam
ajcrm125@gmail.com
...Re: Using EDIF file in XPS
Laurent Gauch - 2005-07-20 04:16:00
Hi Mohsen,
Synplify Pro is able to generate output netlist in EDIF / VHDL / Verilog.
You have to change your script of Synplify Pro for generating the VHDL
output netlist.
Otherway, you will need to have an EDIF2VHDL converter. Please contact
me, I have written a EDIF2VHDL in perl languag...using C/C++ with microblaze
jeanronald - 2007-11-11 15:32:00
I don't understand the link between my hdl ip and the C code, How can I
access a port declared using vhdl using c code.
...32 bit convolution with vhdl
vickey_18 - 2008-02-20 08:18:00
Hello All
I am currently working on a design in which I have to perform a 32 bit
convolution. Can anyone give any ideas of doing this with maximum parallel
processing so device utilization is minimum??
Thank You.
...Re: Look for a microprocessor trainer
Hans - 2005-09-17 03:35:00
What about making your own board? You can find many free FPGA
implementations of 8/16 bits processors on the web. You can buy an FPGA
prototype board + development tools for less than $150 (e.g.
http://www.terasic.com/english/fpga_01.htm).
Some examples:
6809 http://members.optushome.com...Xilinx VSK (Video Starter Kit)
dakkumar - 2006-09-03 01:54:00
I would like to exchange information on the Xilinx VSK with others
using the kit.
In particular I have the following observations:
A1. The VSK provides no help to people who do not wish to invest in (a)
Matlab, (b) Simulink, (c) ISE 8.1, and (d) an MXE version compatible
with 8.1. VSK assum...Re: Smallest system you've ever worked on?
Guy Macon - 2004-04-29 15:57:00
rickman says...
> I always wanted to implement a microcoded Forth on this machine.
> But I could never get the docs on the microcode. Now it would
> be much easier and faster to use an FPGA.
_Implementing a Forth Engine Microcontroller on a Xilinx FPGA_
Richard E. Haskell and Darrin M. ...Re: FPGA + Microcontroller - HELP
jetmarc - 2004-10-22 08:02:00
> > Does anyone know the price for FPSLICs? (largest ones)
>
> Devices are fairly cheap ( ...JTAG implementation
Giovanni - 2004-04-06 05:09:00
Hello everybody. I'm interested in developing a JTAG system using a FPGA
programmed in VHDL. Is there some good source on line that can help me
in doing that? Where can I found the specification of JTAG standard? Are
they free available?
...Re: Tiny dual port RAM needed
Eric - 2005-06-02 16:59:00
A $1.00 CPLD from Xilinx or Altera would do the job. You would just
have to code up a little VHDL or Verilog to define the dual port ram
function.
Eric
...primeview tft lcd
Frank van Eijkelenburg - 2006-03-17 06:28:00
We want to use the primeview tft lcd (PW045XS1). I looked at the datasheet, but it is very summerary. Does anyone know where I can get more
information or perhaps example code of how to use this lcd. I have to make my own display controller in vhdl, but example code in C would be also
helpfull.
...32 bit uart
athulyapg - 2007-10-17 09:40:00
Hi
Im trying to implement an 32bit Uart in cyclone 2 fpga(ep2c8t144).
My requirements are as follows:
speed: 9600bps
In built fifo(depth 8)at transmitter and receiver side.
DMA and Modem controller not required.
Can anyone help me with a vhdl code.
...Embedded systems + VHDL on FPGA home project
cloud9ine - 2007-07-24 08:35:00
My hello to all members out there. I have great interest in embedded
systems and networking, and have worked on an 8051-based platform for over
2 years as part of my Master's research (C programming).
Unfortunately, my job (first job ever) doesn't have anything to do with
embedded so I want to st...