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Verilog

Comp.Arch.Embedded is a worldwide Usenet news group that is used to discuss various aspects of Embedded Systems development.

We found 119 threads matching "verilog"

You are looking at page 1 of 3.

The most relevant threads are listed first

Verilog Simulator

ngsayjoe@gmail.com - 22:43 22-05-06
Hi, all I recently developed a Verilog Simulator for Windows-platform. It's called LogicSim and is free for the time being. It supports most of the Verilog-2001 constructs, and has a very good Verilog text editor and development environment. I'm currently in the process of adding a waveform e...Verilog Simulator

Verilog modeling.

Artem - 02:35 30-03-05
Hi all. I have a "Verilog Behavioral Model of Synchronous 128M SDRAM". I have a Quartus II. How I can use this model in this software? I have read in manual that verilog simulation is not supported by quartus. ...Verilog modeling.

Icarus Verilog for Windows

Pablo Bleyer Kocik - 09:12 09-07-04
Hello people. I will be maintaining recent snapshots of the Icarus Verilog compiler for the Windows platform in easy to use installers at http://armoid.com/icarus/. I have been doing this for more than a year now for the people in my company so I thought, what the heck, for the same effort I...Icarus Verilog for Windows

Converting C-style include file to Verilog?

Frank Miles - 14:14 13-01-05
I have a system that includes both C (for a microprocessor) and Verilog code. Where these components interact, I would like to have a single source file from which certain relevant constants are derived. Initially, at least, I'm looking for a way to simply generate a Verilog file from a 'C' i...Converting C-style include file to Verilog?

VHDL/Verilog Book Recomendations?

PagCal - 05:19 19-01-06
What would be the best starter book for learning both VHDL and Verilog? As well, the book should talk about design techniques of CPLD's and FPGA's. ...VHDL/Verilog Book Recomendations?

Probelms simulating Xilinx FFT version 3.2 core in ModelSim SE

makhan - 00:33 11-04-08
Hello, I am using Xilinx 9.1i and Modelsim 5.7g. I instantiated a coregen module for FFT ver 3.2. After successfully synthesizing the module with the generated xco, I am now trying to simulate the module. The hierarchy is as follows: fft_tb => fft_top => fft.v (generated by coregen) I am...Probelms simulating Xilinx FFT version 3.2 core in ModelSim SE

What graphical entry/documentation tools?

jamesp - 11:36 08-12-05
Hi, I am a mature student will be doing some complex VHDL and Verilog design work for my course. As well as having to create and test the functionality of the design (in both languages) I want to document how the design is put together and it's complex hierarchy. Is there anything out th...What graphical entry/documentation tools?

VHDL and Verilog - 15 x Contract Engineers Required Urgently - Long Term Contract

Specialist Verilog Engineers Roles - 09:28 27-06-07
My client is an award winning leader in their global field, and looking to expand their broadcast engineering team. If you are an engineer with strong Verilog VHDL experience then we would like to hear from you. C++ and FPGA experience would be a nice to have. If you want to be part of an unriva...VHDL and Verilog - 15 x Contract Engineers Required Urgently - Long Term Contract

ASIC verification job info request

Dwayne Dilbeck - 15:06 19-12-07
I am looking for a reality check. I have 10 years experience doing software verification on EDA tools, in particular hardware emulators, System Verilog, and VHDL. When looking at some job ads I see "required 6+ years ASIC verification experience", can any of my 10 years experience be con...ASIC verification job info request

Re: Editor?

Tim Wescott - 00:40 03-01-05
Guy Macon wrote: > MetalHead wrote: > > > > I've been using UltraEdit and have been really happy with it. You can > > configure almost everything about it and it works with large files. > > supports all the usual syntax coloring and such (if you want it) and has > > been extremely rel...Re: Editor?

ANNC: Verilog Coding for FPGA Webcast

bart - 19:32 08-04-08
Lattice is holding a webcast tomorrow, Wednesday, April 9, "Optimizing Verilog Coding for More Efficient FPGA Synthesis." The presenter will be Troy Scott, from our software marketing group. If you're interested, the event takes place live at 11am Pacific, 18:00 GMT. In addition, you will be a...ANNC: Verilog Coding for FPGA Webcast

Re: what is system C.

Hans - 04:51 22-10-06
SystemC is a concurrent (parallel) language similar to languages like VHDL and Verilog whereas C is an untimed sequential language. SystemC doesn't "generate" synthesisable descriptions, for that you need a SystemC synthesis tool like Celoxica's Agility. If you are thinking of using an FPGA...Re: what is system C.

Re: FPGA for hobbyist ??

Rich Webb - 18:49 19-04-05
On Mon, 18 Apr 2005 23:15:13 -0700, nets wrote: > > Just wondering, does hobbyist with fund less than USD200/month could > > afford playing with FPGA ? > > There is a starting point: > > http://www.digilentinc.com > http://www.xilinx.com/products/design_resources/design_tool/index.htm ...Re: FPGA for hobbyist ??

Re: need help on a 8051 ip core

Joe - 14:57 27-07-04
jpmcg wrote: > Hi there folks i`m currently doing a msc project and trying to > implement a 8051 ip core and program it using 'C'. Porblem is i cant > find an ip core that will let me use it without having to spend money > on it. As i am a student i cant get my hands on that kind of cash....Re: need help on a 8051 ip core

I2C master connected and tested with LEON Processor

Pinhas - 06:04 10-08-07
This design uses the open core's I2C master. The core's CPU interface is modified from WISHBONE to AMBA/APB. The latter is done in order to test the core and its new APB interface with LEON processor. LEON is written in VHDL therefor the core's VHDL RTL design is tested. The core also...I2C master connected and tested with LEON Processor

RTL for Z8000 series CPU?

ajcrm125 - 14:24 22-12-05
Hey guys, does anyone know where I can get VHDL/Verilog source for the Z8001/Z8002 processor? Thanks for any info! -Adam ajcrm125@gmail.com ...RTL for Z8000 series CPU?

Re: system level language: why all this fuss about

Kevin Neilson - 16:53 07-04-08
Karl wrote: > why all this fuss ... > > thanks I definitely think more abstraction is important, but I don't see the need for a new language. Like Kolja points out, the languages we have now are fine. There is plenty of abstractability in Verilog that is not supported by synthesizer...Re: system level language: why all this fuss about

Re: FPGA Development Board

Matthew Hicks - 16:01 05-07-07
I wasn't going to spend my time correcting the response by samiam, but I have to now because some moron wants to waste eveyone's time by quiping, "I've never heard of Xylinx." Way to go loser, ha ha, he said Xylinx when it is really supposed to be Xilinx. If that's all you have to add, next ...Re: FPGA Development Board

Xilinx VSK (Video Starter Kit)

dakkumar - 01:54 03-09-06
I would like to exchange information on the Xilinx VSK with others using the kit. In particular I have the following observations: A1. The VSK provides no help to people who do not wish to invest in (a) Matlab, (b) Simulink, (c) ISE 8.1, and (d) an MXE version compatible with 8.1. VSK assum...Xilinx VSK (Video Starter Kit)

Re: Tiny dual port RAM needed

Eric - 16:59 02-06-05
A $1.00 CPLD from Xilinx or Altera would do the job. You would just have to code up a little VHDL or Verilog to define the dual port ram function. Eric ...Re: Tiny dual port RAM needed

pci wishbone, can ip core

mungam - 08:11 10-03-06
Hello, I have a can ip core in verilog, I'm willing to implement it on a fpga PCI board. To do that I have to make a "PCI wishbone" but I don't know it what it consists exactly and how to do it. I have seen some articles about that on opencores.org but my english is poor and I'm a little ...pci wishbone, can ip core

Re: engineering graduate school question

cpope - 13:35 28-06-07
I doubt anyone is reading this thread anymore, but I can't let the posts that are marginalizing formal education stand. Maybe it's cognitive dissonance that I don't want to admit I've wasted time/money in school, but I think it's more some of these comments smack of the "I don't need no schoolin...Re: engineering graduate school question

Re: Getting started VHDL, VHDL for Dummies, Easy Steps for FPGA experiments

Kevin Brace - 18:03 25-09-05
Hi Kutaj, I recommend downloading free Xilinx ISE WebPACK design software from Xilinx since at least Xilinx gives you a very slow HDL simulator (ModelSim XE-Starter) unlike Altera, Actel, or Lattice. I believe ModelSim XE-Starter supports Windows only, so I recommend sticking to Windows fo...Re: Getting started VHDL, VHDL for Dummies, Easy Steps for FPGA experiments

Software to generate jed file for PAL chips

CFF - 00:39 13-03-04
Hi, I need to program a couple of old small assorted brand PAL (including GAL) chips. Is there any free software tool that can generate jed files from Verilog (or ABEL and schematic) entry so that I can export to a universal programmer for downloading purpose? Thanks for any help. CFF ...Software to generate jed file for PAL chips

FIFO hdl code

11:00 12-08-05
Hi, I need to stream audio data and control info I2C out of my PC into some external hardware and was thinking of using a FIFO to deal with the different clock boundaries. I was wondering if anyone had some startup verilog code on FIFOs, I am using a Xilinx FPGA Thanks Ryan (ryan.pinto7...FIFO hdl code

Re: PAL

Kelly Hall - 22:34 18-08-05
cr0acker wrote: > Can anyone tell me which software was used to compile following code > into burnable PAL 16L8 image? Doesn't look like PALASM, CUPL, or ABEL. It's certainly not VHDL or Verilog. Maybe one of the proprietary languages that PAL vendors each seemed to have back in the day...Re: PAL

best way to simulate multi core architecture ?

TheWhizKid - 19:48 24-09-05
Hi guys, Please give me some suggestions ! 1. I need to make a cycle accurate simulator for a dual core cpu. How do I pass external events like interrupts from one core to another during the simulation ? 2. How does one make a "C" reference model talk to a verilog model during...best way to simulate multi core architecture ?

Re: learn FPGA / CPLD - tools / books?

maxfoo - 19:38 02-04-04
On 2 Apr 2004 10:01:28 -0800, yqin_99@yahoo.com (yong) wrote: > Can anyone recommend a good book for learn FPGA/CPLD programming? > here's a free one in Verilog HDL. http://www.sutherland-hdl.com/on-line_ref_guide/vlog_ref_top.html > Any low price develop tools? No. Remove "HeadF...Re: learn FPGA / CPLD - tools / books?

Re: Logic simulator?

Rich Webb - 23:13 06-09-04
On Mon, 6 Sep 2004 18:45:38 -0700, "Neil Bradley" wrote: > Can anyone recommend a Windows based (freeware preferable) logic simulator > program? I really could use one for an embedded system I'm designing (with > some very sticky decode and select logic). Everything I've found so far is ...Re: Logic simulator?

Re: Core module

leaf - 01:04 17-03-06
If what you're saying is about core modules for CPLD/FPGA then it is a design (VHDL/Verilog ect.) like: PCI Core (PCI Interface Module) - used to allow interfacing of your custom card to PCI PCI Express Module MicroBlaze... etc. So instead of creating these modules you will just snap it wit...Re: Core module

Re: what is Back-annotate?

Adrian - 09:23 16-02-06
Quartus II is an FPGA design program from Altera. Back-annotation means that after synthesizing and generating the layout of your device, the real time delays are determined and put back to the original design. This will let you redo the VHDL/Verilog simulation using the real timing compared ...Re: what is Back-annotate?

Re: Microcontroller USB interface chip

pinik - 06:24 05-05-08
> On May 1, 4:00 pm, mach7 wrote: > > I know very little about USB, so excuse the naive question. I'm > > looking for an IC that I can interface with a microcontroller (in my > > case, the ATMega32) that will let me communicate with a computer over > > USB. My project involves large dat...Re: Microcontroller USB interface chip

Re: synopsys tool help newsgroup

Arlet - 13:22 25-01-08
On Jan 25, 5:21 pm, Pasacco wrote: > dear > > I think this is not a proper group, > > But I am looking for a group to discuss "how to use synopsys tool and > how to trouble-shoot" > > If anyone knows, please let me know (for example newsgroup). Try comp.arch.fpga, or comp.lang....Re: synopsys tool help newsgroup

Final Year Project in FPGA

UETIAN - 14:49 14-10-06
Hello: I want to know about hot fields of working in FPGA.I am doing computer engineering and want to do FPGA related project.I also want to learn about the sub fields in FPGA.I have a good command in verilog but nearly zero knowledge about FPGA's.Please give me data related with FPGA p...Final Year Project in FPGA

Re: CPU design

Antti - 05:37 25-08-06
jacko schrieb: > jacko wrote: > > hi > > > > got altera quartus II > > > > http://indi.joox.net as my site > > trying to make simple MISC design for embedded and stand alone. > > > > cheesr > > Quartus II design files for 24 blue block on cyclone II 16 bit CPU. (no >...Re: CPU design

Re: HC11 Transistor Architecture

14:31 02-11-05
Grant Edwards wrote: > Is RTL synthesizable, or is it just for simulation? RTL isn't a specific language, it's a level of abstraction. I'm not sure of a formal definition, but in general it involves defining registers and the data paths and conbinatorial logic that links them. RTL code wo...Re: HC11 Transistor Architecture

Re: Half a Century of Crappy Computing

Traveler - 20:35 05-11-07
On Mon, 05 Nov 2007 12:31:09 -0500, "Eric P." wrote: [cut] > Has anyone ever produced a proven correct system with it? > (Something non-trivial like an elevator control with > a capacity optimized route scheduler.) Well, consider that VHDL and Verilog are synchronous reactive systems....Re: Half a Century of Crappy Computing

Re: LEGO mindstorms and FPGA

Alex Gibson - 23:26 07-08-04
"Martin Schoeberl" wrote in message news:CA4Rc.45883$M72.19963@news.chello.at... > Yesterday I bought a LEGO mindstorms set (getting infantil in my old > days...). After building the first robot, I want to substitue the RCX by > an FPGA. Has anyone done this so far? > Not that I've ...Re: LEGO mindstorms and FPGA

Re: Bit width?

Ulf Samuelsson - 13:35 03-06-04
"Rick Merrill" skrev i meddelandet news:3ntvc.38175$js4.36927@attbi_s51... > Meindert Sprang wrote: > > Reading about buses, processors and memories being n bits wide makes me > > wonder: how wide is one bit? > > > > Meindert > > A Quantum bit (called a Qbit) has three stat...Re: Bit width?

Re: Self restarting property of RTOS-How it works?

Elder Costa - 17:03 10-02-05
del cecchi wrote: > > Like hardware doesn't have bugs or "errata". Go check Intel's web > site. > > Especially new hardware. sheesh > First of all, I dare to say this kind of hardware is mostly if not totaly software as these processors are synthesized from (Verilog? VHDL?) bui...Re: Self restarting property of RTOS-How it works?
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