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Verilog
Comp.Arch.Embedded is a worldwide Usenet news group that is used to discuss various aspects of Embedded Systems development.
We found 144 threads matching "verilog"
You are looking at page 1 of 4.
The most relevant threads are listed first
Verilog Simulator
ngsayjoe@gmail.com - 2006-05-22 22:43:00
Hi, all
I recently developed a Verilog Simulator for Windows-platform. It's
called LogicSim and is free for the time being. It supports most of the
Verilog-2001 constructs, and has a very good Verilog text editor and
development environment.
I'm currently in the process of adding a waveform e...
Verilog modeling.
Artem - 2005-03-30 02:35:00
Hi all.
I have a "Verilog Behavioral Model of Synchronous 128M SDRAM". I have a
Quartus II. How I can use this model in this software? I have read in
manual that verilog simulation is not supported by quartus.
...C-to-Verilog for embedded designs
Nadav Rotem - 2008-12-14 14:31:00
Hello,
My name is Nadav and I operate the website http://www.c-to-verilog.com
; In the website people can cut-and-paste their C code and it will
"compile" and synthesize it into a Verilog module. You can later
synthesize the core to an FPGA and connect it to a SoC design. The
generated Veril...Icarus Verilog for Windows
Pablo Bleyer Kocik - 2004-07-09 09:12:00
Hello people.
I will be maintaining recent snapshots of the Icarus Verilog compiler
for the Windows platform in easy to use installers at
http://armoid.com/icarus/. I have been doing this for more than a year
now for the people in my company so I thought, what the heck, for the
same effort I...Converting C-style include file to Verilog?
Frank Miles - 2005-01-13 14:14:00
I have a system that includes both C (for a microprocessor) and Verilog
code. Where these components interact, I would like to have a single
source file from which certain relevant constants are derived. Initially,
at least, I'm looking for a way to simply generate a Verilog file from
a 'C' i...VHDL/Verilog Book Recomendations?
PagCal - 2006-01-19 05:19:00
What would be the best starter book for learning both VHDL and Verilog?
As well, the book should talk about design techniques of CPLD's and FPGA's.
...SDIO verilog master
beky4kr@gmail.com - 2008-11-28 14:43:00
h--p://bknpk.no-ip.biz/SDIO/Commercial.html
The following will describe the operation, which is done by the SDIO
verilog master....
...Probelms simulating Xilinx FFT version 3.2 core in ModelSim SE
makhan - 2008-04-11 00:33:00
Hello,
I am using Xilinx 9.1i and Modelsim 5.7g. I instantiated a coregen
module for FFT ver 3.2. After successfully synthesizing the module
with the generated xco, I am now trying to simulate the module. The
hierarchy is as follows:
fft_tb => fft_top => fft.v (generated by coregen)
I am...Re: Memory Test algorithm
Marcus Harnisch - 2008-09-19 05:34:00
WiMos writes:
> Try googling for "march B" or "march C" memory tests.
> These are the best I could find.
And while googling anyway, add "march cw" to the list.
Regards
Marcus
--
note that "property" can also be used as syntaxtic sugar to reference
a property, breaking the clean d...What graphical entry/documentation tools?
jamesp - 2005-12-08 11:36:00
Hi,
I am a mature student will be doing some complex VHDL and Verilog design
work for my course. As well as having to create and test the
functionality of the design (in both languages) I want to document how
the design is put together and it's complex hierarchy.
Is there anything out th...VHDL and Verilog - 15 x Contract Engineers Required Urgently - Long Term Contract
Specialist Verilog Engineers Roles - 2007-06-27 09:28:00
My client is an award winning leader in their global field, and
looking to expand their broadcast engineering team. If you are an
engineer with strong Verilog VHDL experience then we would like to
hear from you. C++ and FPGA experience would be a nice to have. If you
want to be part of an unriva...ASIC verification job info request
Dwayne Dilbeck - 2007-12-19 15:06:00
I am looking for a reality check. I have 10 years experience doing
software verification on EDA tools, in particular hardware emulators, System
Verilog, and VHDL. When looking at some job ads I see "required 6+ years
ASIC verification experience", can any of my 10 years experience be
con...Re: Editor?
Tim Wescott - 2005-01-03 00:40:00
Guy Macon wrote:
> MetalHead wrote:
>
>
> > I've been using UltraEdit and have been really happy with it. You can
> > configure almost everything about it and it works with large files.
> > supports all the usual syntax coloring and such (if you want it) and has
> > been extremely rel...ANNC: Verilog Coding for FPGA Webcast
bart - 2008-04-08 19:32:00
Lattice is holding a webcast tomorrow, Wednesday, April 9, "Optimizing
Verilog Coding for More Efficient FPGA Synthesis." The presenter will
be Troy Scott, from our software marketing group.
If you're interested, the event takes place live at 11am Pacific,
18:00 GMT. In addition, you will be a...Re: what is system C.
Hans - 2006-10-22 04:51:00
SystemC is a concurrent (parallel) language similar to languages like VHDL
and Verilog whereas C is an untimed sequential language. SystemC doesn't
"generate" synthesisable descriptions, for that you need a SystemC synthesis
tool like Celoxica's Agility.
If you are thinking of using an FPGA...Re: FPGA for hobbyist ??
Rich Webb - 2005-04-19 18:49:00
On Mon, 18 Apr 2005 23:15:13 -0700, nets wrote:
> > Just wondering, does hobbyist with fund less than USD200/month could
> > afford playing with FPGA ?
>
> There is a starting point:
>
> http://www.digilentinc.com
> http://www.xilinx.com/products/design_resources/design_tool/index.htm
...Re: need help on a 8051 ip core
Joe - 2004-07-27 14:57:00
jpmcg wrote:
> Hi there folks i`m currently doing a msc project and trying to
> implement a 8051 ip core and program it using 'C'. Porblem is i cant
> find an ip core that will let me use it without having to spend money
> on it. As i am a student i cant get my hands on that kind of cash....I2C master connected and tested with LEON Processor
Pinhas - 2007-08-10 06:04:00
This design uses the open core's I2C master. The core's CPU interface
is
modified from WISHBONE to AMBA/APB. The latter is done in order to
test the
core and its new APB interface with LEON processor. LEON is written in
VHDL
therefor the core's VHDL RTL design is tested.
The core also...RTL for Z8000 series CPU?
ajcrm125 - 2005-12-22 14:24:00
Hey guys, does anyone know where I can get VHDL/Verilog source for the
Z8001/Z8002 processor?
Thanks for any info!
-Adam
ajcrm125@gmail.com
...Re: system level language: why all this fuss about
Kevin Neilson - 2008-04-07 16:53:00
Karl wrote:
> why all this fuss ...
>
> thanks
I definitely think more abstraction is important, but I don't see the
need for a new language. Like Kolja points out, the languages we have
now are fine. There is plenty of abstractability in Verilog that is not
supported by synthesizer...Re: FPGA Development Board
Matthew Hicks - 2007-07-05 16:01:00
I wasn't going to spend my time correcting the response by samiam, but I
have to now because some moron wants to waste eveyone's time by quiping,
"I've never heard of Xylinx." Way to go loser, ha ha, he said Xylinx when
it is really supposed to be Xilinx. If that's all you have to add, next ...Xilinx VSK (Video Starter Kit)
dakkumar - 2006-09-03 01:54:00
I would like to exchange information on the Xilinx VSK with others
using the kit.
In particular I have the following observations:
A1. The VSK provides no help to people who do not wish to invest in (a)
Matlab, (b) Simulink, (c) ISE 8.1, and (d) an MXE version compatible
with 8.1. VSK assum...Re: Tiny dual port RAM needed
Eric - 2005-06-02 16:59:00
A $1.00 CPLD from Xilinx or Altera would do the job. You would just
have to code up a little VHDL or Verilog to define the dual port ram
function.
Eric
...Re: ARM AMBA Designer licensing cost
Marcus Harnisch - 2008-11-02 13:19:00
"guestuser1" writes:
> A different department at my company handles the ARM licensing.
> I think we need to generate some AHB/AXI interconnect blocks,
> but in order to produce the synthesizeable RTL, we need an
> AMBA_Designer license. (We already have an SOC designer,
> ARM compile...pci wishbone, can ip core
mungam - 2006-03-10 08:11:00
Hello,
I have a can ip core in verilog, I'm willing to implement it on a fpga
PCI board. To do that I have to make a "PCI wishbone" but I don't know
it what it consists exactly and how to do it. I have seen some articles
about that on opencores.org but my english is poor and I'm a little ...Re: For exact data transfer by using FT2232H .
Paul Ham - 2009-06-10 02:01:00
> Paul Ham schreef:
> > ...
> >
==============================================================================
> >
> > Many thanks to your concern.
> >
> > But, actually, I haven`t found a good solution yet.
> >
> > I have tried like below :
> >
> > 1) Reinstalling a Driver f...Re: Recommended GPL-Spice under linux ?
2008-11-13 11:41:00
problems@gmail writes:
> Please advise what/where I may test Spice under linux.
Perhaps http://www.geda.seul.org/tools/ngspice/ ?
gEDA has two other simulators too - verilog and gnucap.
...Re: engineering graduate school question
cpope - 2007-06-28 13:35:00
I doubt anyone is reading this thread anymore, but I can't let the posts
that are marginalizing formal education stand. Maybe it's cognitive
dissonance that I don't want to admit I've wasted time/money in school, but
I think it's more some of these comments smack of the "I don't need no
schoolin...Re: Getting started VHDL, VHDL for Dummies, Easy Steps for FPGA experiments
Kevin Brace - 2005-09-25 18:03:00
Hi Kutaj,
I recommend downloading free Xilinx ISE WebPACK design software from
Xilinx since at least Xilinx gives you a very slow HDL simulator
(ModelSim XE-Starter) unlike Altera, Actel, or Lattice.
I believe ModelSim XE-Starter supports Windows only, so I recommend
sticking to Windows fo...Software to generate jed file for PAL chips
CFF - 2004-03-13 00:39:00
Hi,
I need to program a couple of old small assorted brand PAL (including
GAL) chips. Is there any free software tool that can generate jed
files from Verilog (or ABEL and schematic) entry so that I can export
to a universal programmer for downloading purpose? Thanks for any
help.
CFF
...FIFO hdl code
2005-08-12 11:00:00
Hi, I need to stream audio data and control info I2C out of my PC into
some external hardware and was thinking of using a FIFO to deal with
the different clock boundaries.
I was wondering if anyone had some startup verilog code on FIFOs, I am
using a Xilinx FPGA
Thanks
Ryan
(ryan.pinto7...Re: PAL
Kelly Hall - 2005-08-18 22:34:00
cr0acker wrote:
> Can anyone tell me which software was used to compile following code
> into burnable PAL 16L8 image?
Doesn't look like PALASM, CUPL, or ABEL. It's certainly not VHDL or
Verilog. Maybe one of the proprietary languages that PAL vendors each
seemed to have back in the day...best way to simulate multi core architecture ?
TheWhizKid - 2005-09-24 19:48:00
Hi guys, Please give me some suggestions !
1. I need to make a cycle accurate simulator for a
dual core cpu. How do I pass external events like
interrupts from one core to another during the
simulation ?
2. How does one make a "C" reference model talk to a verilog
model during...audio fingerprinting using fpga
vibz86 - 2009-11-07 00:27:00
Hi, I have to implement audio fingerprinting in fpga using verilog. As Im
new to fpga, Im finding it hard to start with this. Can someone send me any
sample codes of audio fingerprinting or any usefull links that will help me
to learn and do this project quickly
-----------------------...Re: learn FPGA / CPLD - tools / books?
maxfoo - 2004-04-02 19:38:00
On 2 Apr 2004 10:01:28 -0800, yqin_99@yahoo.com (yong) wrote:
> Can anyone recommend a good book for learn FPGA/CPLD programming?
>
here's a free one in Verilog HDL.
http://www.sutherland-hdl.com/on-line_ref_guide/vlog_ref_top.html
> Any low price develop tools?
No.
Remove "HeadF...Re: Logic simulator?
Rich Webb - 2004-09-06 23:13:00
On Mon, 6 Sep 2004 18:45:38 -0700, "Neil Bradley"
wrote:
> Can anyone recommend a Windows based (freeware preferable) logic simulator
> program? I really could use one for an embedded system I'm designing (with
> some very sticky decode and select logic). Everything I've found so far is
...Re: Core module
leaf - 2006-03-17 01:04:00
If what you're saying is about core modules for CPLD/FPGA then
it is a design (VHDL/Verilog ect.) like:
PCI Core (PCI Interface Module)
- used to allow interfacing of your custom card to PCI
PCI Express Module
MicroBlaze...
etc.
So instead of creating these modules you will just snap it wit...free cpu 8051 verilog code
Pinhas - 2008-10-15 10:05:00
http://bknpk.no-ip.biz/cpu_8051_ver/top.html
#
Stable Design: The design is translated from a VHDL dalton project
http://www.cs.ucr.edu/~dalton/i8051/i8051syn.
#
Small Design: Consumes only 324 Flip-Flops: map report
#
Fast Design: 50MHz for a xc4vlx25-10 XILINX device: timing report
...Re: what is Back-annotate?
Adrian - 2006-02-16 09:23:00
Quartus II is an FPGA design program from Altera.
Back-annotation means that after synthesizing and generating the layout
of your device, the real time delays are determined and put back to
the original design. This will let you redo the VHDL/Verilog simulation
using the real timing compared ...interfacing a xilinx FPGA with a coldfire processor
dargo - 2009-01-03 09:37:00
Hi,
I'm looking for advice to implement on my FPGA (Xilinx SPARTAN 3A) a VHDL
interface with an external COLDFIRE processor. Due to hardware
considerations (not mine) I need to use 9 bits of address and 16 bits of
datas,
The following signals are available on my incoming pinout : TA, TEA, CS1,
IRQ...