Den söndagen den 8:e juli 2012 kl. 03:09:06 UTC+2 skrev Andrew Smallshaw:
> On 2012-07-07, l...@gmail.com <l...@gmail.com> wrote:
> > Den l?rdagen den 7:e juli 2012 kl. 20:20:57 UTC+2 skrev Andrew Smallshaw:
> >> I'm considering a project here where I'll need a reasonable amount
> >> of storage in an otherwise "small" system.  The spec hasn't been
> >> firmed up yet but I imagine we're looking at a 16 bitter CPU,
> >> probably a PIC18 or an MSP430.  "Reasonable" storage in this context
> >> means no more than 100MB.  Volatility isn't a problem but the
> >> rewrite cycles are such I'd be wary of flash storage, so I'm finding
> >> myself drawn towards a RAM disk - i.e. not directly addressable
> >> memory but something that can be accessed after the requisite port
> >> set up.
> >
> > Why not a SRAM 128k x 8  or 512k x 8 ?
> 
> We'd be talking hundreds of chips to get the required capacity.
> I think some off the shelf board is going to be the answer here
> but I'll have to have a good look around for something that fits
> the form factor - I'm constrained in width more than anything else.
> The space available is approximately 10"x3"x1.5".
> 
> -- 
> Andrew Smallshaw
> a...@sdf.lonestar.org

Sorry, too late at night, the brain was already switched off ... 

On 07/07/2012 19:20, Andrew Smallshaw wrote:
> I'm considering a project here where I'll need a reasonable amount
> of storage in an otherwise "small" system.  The spec hasn't been
> firmed up yet but I imagine we're looking at a 16 bitter CPU,
> probably a PIC18 or an MSP430.  "Reasonable" storage in this context
> means no more than 100MB.  Volatility isn't a problem but the
> rewrite cycles are such I'd be wary of flash storage, so I'm finding
> myself drawn towards a RAM disk - i.e. not directly addressable
> memory but something that can be accessed after the requisite port
> set up.
>
> Looking at memories the pricing of commodity DDR2/3 DIMMs are
> certainly very attractive but I'm a little hesitant over the
> interfacing requirements - I'm used to operating at a few tens of
> MHz, no more than double-sided PCBs and I know next to nothing of
> transmission lines.  Can these memories be underclocked to that
> extent and still behave nicely, or does anyone have other insights?
>
About the only way you can do this with a small processor is to use an 
FPGA with an SDRAM. SDRAMs can be seriously underclocked and if you use 
an optimum pinout on the FPGA you can route the FPGA<->SDRAM interface 
on one side of the board - no funny stuff (eg matched track lengths or 
terminations) needed. The processor can access the RAM via the FPGA 
using any interface you like - SPI, //, serial etc etc.
The FPGA task is not that demanding so it need not cost too much.

I know that all this works because I've done it (in more than one 
design). If you want detailed help contact me by email (which you can 
get via my web site www.mkesc.co.uk).


Michael Kellett

On Sat, 7 Jul 2012 18:20:57 +0000 (UTC)
Andrew Smallshaw <a...@sdf.lonestar.org> wrote:

> I'm considering a project here where I'll need a reasonable amount
> of storage in an otherwise "small" system.  The spec hasn't been
> firmed up yet but I imagine we're looking at a 16 bitter CPU,
> probably a PIC18 or an MSP430.  "Reasonable" storage in this context
> means no more than 100MB.  Volatility isn't a problem but the
> rewrite cycles are such I'd be wary of flash storage, so I'm finding
> myself drawn towards a RAM disk - i.e. not directly addressable
> memory but something that can be accessed after the requisite port
> set up.
> 
> Looking at memories the pricing of commodity DDR2/3 DIMMs are
> certainly very attractive but I'm a little hesitant over the
> interfacing requirements - I'm used to operating at a few tens of
> MHz, no more than double-sided PCBs and I know next to nothing of
> transmission lines.  Can these memories be underclocked to that
> extent and still behave nicely, or does anyone have other insights?
> 
> -- 
> Andrew Smallshaw
> a...@sdf.lonestar.org

I second lots of other people's answers re: SDRAM over DDR.

But this part's interesting: "Volatility isn't a problem but the
rewrite cycles are such I'd be wary of flash storage".  So it's not
obviously dealbreaking, just worrisome.  So what about a LOT of flash?

Digikey will sell you 8Gb NAND flash chips for about $16.  Wear leveling
100Mb over that gives you another factor of 80 overtop the native 100K
cycles.  That's a whole lot of ins and outs.

Or possibly some interchangable storage, like an SD card, that you
simply replace every now and again.

-- 
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order.  See above to fix.

Andrew Smallshaw <a...@sdf.lonestar.org> writes:

> Looking at memories the pricing of commodity DDR2/3 DIMMs are
> certainly very attractive but I'm a little hesitant over the
> interfacing requirements - I'm used to operating at a few tens of
> MHz, no more than double-sided PCBs and I know next to nothing of
> transmission lines.  Can these memories be underclocked to that
> extent and still behave nicely, or does anyone have other insights?


DDR memory requires fast signaling and basically always a memory
controller. In one project we used Micron Mobile SDRAMs that have
a self-refresh functionality. A quick search from Digikey gave
MT48H4M16LF as an example.

-- 
Mikko

What about a AVR32UC3 device that has an internal SDRAM controller? We
use one of those running at 20Mhz along with a 64MB SDRAM from Micron.
It's a 32 bit CPU but who cares, it's low power.

In article <f...@bt.com>,
MK  <m...@nospam.co.uk> wrote:
<SNIP>
>About the only way you can do this with a small processor is to use an
>FPGA with an SDRAM. SDRAMs can be seriously underclocked and if you use

What do you mean by this? That they still work with a clock speed that is
substantially below the maximum specified speed?

>an optimum pinout on the FPGA you can route the FPGA<->SDRAM interface
>on one side of the board - no funny stuff (eg matched track lengths or
>terminations) needed. The processor can access the RAM via the FPGA
>using any interface you like - SPI, //, serial etc etc.
>The FPGA task is not that demanding so it need not cost too much.

>
>
>Michael Kellett
>

Groetjes Albert

--
-- 
Albert van der Horst, UTRECHT,THE NETHERLANDS
Economic growth -- being exponential -- ultimately falters.
albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst

On 10/07/2012 16:17, Albert van der Horst wrote:
> In article <f...@bt.com>,
> MK  <m...@nospam.co.uk> wrote:
> <SNIP>
>> About the only way you can do this with a small processor is to use an
>> FPGA with an SDRAM. SDRAMs can be seriously underclocked and if you use
>
> What do you mean by this? That they still work with a clock speed that is
> substantially below the maximum specified speed?
>
>> an optimum pinout on the FPGA you can route the FPGA<->SDRAM interface
>> on one side of the board - no funny stuff (eg matched track lengths or
>> terminations) needed. The processor can access the RAM via the FPGA
>> using any interface you like - SPI, //, serial etc etc.
>> The FPGA task is not that demanding so it need not cost too much.
>
>>
>>
>> Michael Kellett
>>
>
> Groetjes Albert
>
> --
>
Yes - sorry perhaps not perfectly clear - I'm not advocating running 
them outside spec but just making use of the fact that the minimum clock 
speed is very much lower than the maximum. This is not the case with 
DDRAMs where the slowest specified operating frequency is still quite fast.

Michael Kellett

Andrew
DDRx memories use SSTL logic levels and require lots of understanding to get right. Because they are double data rate they have PLLs within, hence the need to go at a minimum speed to keep them locked. They are also BGAs.
SDRAM is 3v3 CMOS and you can put them on busses with any other stuff and generally abuse them. They don't have to be BGAs. I presume that you plan to interface via a CPLD because your PIC18 or whatever certainly won't do it directly. If you choose something like a MAX2 you wouldn't need any new power supplies but they are BGAs.

Colin