I plan to use open collector gates on a serial bus on backplane for
communication between cards. Bus access is some sort of TDMA. What is
the maximum speed that I can go for, assuming there is only one pullup
? Also, which technology would be better - LS, HC or something else. I
feel the rise time limitation would be due to pull up and the gate
capacitance. Please comment.

m...@gmail.com wrote:

> I plan to use open collector gates on a serial bus on backplane for
> communication between cards. Bus access is some sort of TDMA. What is
> the maximum speed that I can go for, assuming there is only one pullup
> ? Also, which technology would be better - LS, HC or something else. I
> feel the rise time limitation would be due to pull up and the gate
> capacitance. Please comment.

Seems you are nearly there. What is the serial speed. Work out the needed
rise time then compare with the rise time due to pull up and gate
capacitance. If the latter is 10 times less than the former you will be OK.

Don't forget to add in back plane track capacitance.

Ian

Ian Bell wrote:
> m...@gmail.com wrote:
>
> > I plan to use open collector gates on a serial bus on backplane for
> > communication between cards. Bus access is some sort of TDMA. What is
> > the maximum speed that I can go for, assuming there is only one pullup
> > ? Also, which technology would be better - LS, HC or something else. I
> > feel the rise time limitation would be due to pull up and the gate
> > capacitance. Please comment.
>
> Seems you are nearly there. What is the serial speed. Work out the needed
> rise time then compare with the rise time due to pull up and gate
> capacitance. If the latter is 10 times less than the former you will be OK.
>
> Don't forget to add in back plane track capacitance.
>
> Ian
Thanks Ian
My serial speed would be 4 Mbits/sec. Power consumption is not a
problem. I wish to use this configuration as a wired-or type of setup.
Should I go for bufferred or non bufferred drive ? Bufferred drivers
have larger sink capacities - allowing smaller pull ups, but have
higher gate capacitance. Also, should I go with CMOS or TTL. As the
gates are OC, the higher drive capacity for logic high would not be
relevant.

m...@gmail.com wrote:

> Ian Bell wrote:
> 
>>m...@gmail.com wrote:
>>
>>
>>>I plan to use open collector gates on a serial bus on backplane for
>>>communication between cards. Bus access is some sort of TDMA. What is
>>>the maximum speed that I can go for, assuming there is only one pullup
>>>? Also, which technology would be better - LS, HC or something else. I
>>>feel the rise time limitation would be due to pull up and the gate
>>>capacitance. Please comment.
>>
>>Seems you are nearly there. What is the serial speed. Work out the needed
>>rise time then compare with the rise time due to pull up and gate
>>capacitance. If the latter is 10 times less than the former you will be OK.
>>
>>Don't forget to add in back plane track capacitance.
>>
>>Ian
> 
> Thanks Ian
> My serial speed would be 4 Mbits/sec. Power consumption is not a
> problem. I wish to use this configuration as a wired-or type of setup.
> Should I go for bufferred or non bufferred drive ? Bufferred drivers
> have larger sink capacities - allowing smaller pull ups, but have
> higher gate capacitance. Also, should I go with CMOS or TTL. As the
> gates are OC, the higher drive capacity for logic high would not be
> relevant.

Have you looked at LVDS ?
-jg

Jim Granville wrote:
> m...@gmail.com wrote:
>
> > Ian Bell wrote:
> >
> >>m...@gmail.com wrote:
> >>
> >>
> >>>I plan to use open collector gates on a serial bus on backplane for
> >>>communication between cards. Bus access is some sort of TDMA. What is
> >>>the maximum speed that I can go for, assuming there is only one pullup
> >>>? Also, which technology would be better - LS, HC or something else. I
> >>>feel the rise time limitation would be due to pull up and the gate
> >>>capacitance. Please comment.
> >>
> >>Seems you are nearly there. What is the serial speed. Work out the needed
> >>rise time then compare with the rise time due to pull up and gate
> >>capacitance. If the latter is 10 times less than the former you will be OK.
> >>
> >>Don't forget to add in back plane track capacitance.
> >>
> >>Ian
> >
> > Thanks Ian
> > My serial speed would be 4 Mbits/sec. Power consumption is not a
> > problem. I wish to use this configuration as a wired-or type of setup.
> > Should I go for bufferred or non bufferred drive ? Bufferred drivers
> > have larger sink capacities - allowing smaller pull ups, but have
> > higher gate capacitance. Also, should I go with CMOS or TTL. As the
> > gates are OC, the higher drive capacity for logic high would not be
> > relevant.
>
> Have you looked at LVDS ?
> -jg

But how to use LVDS in wired-OR type of configuration ? How many
tranceivers can be on multipoint type of configuration for 4 Mbit speed
?

Rakesh

m...@gmail.com wrote:
>>>My serial speed would be 4 Mbits/sec. Power consumption is not a
>>>problem. I wish to use this configuration as a wired-or type of setup.
>>>Should I go for bufferred or non bufferred drive ? Bufferred drivers
>>>have larger sink capacities - allowing smaller pull ups, but have
>>>higher gate capacitance. Also, should I go with CMOS or TTL. As the
>>>gates are OC, the higher drive capacity for logic high would not be
>>>relevant.
>>
>>Have you looked at LVDS ?
>>-jg
> 
> 
> But how to use LVDS in wired-OR type of configuration ? How many
> tranceivers can be on multipoint type of configuration for 4 Mbit speed
> ?

LVDS Rx devices give you differential sense, of a few hundrd mV and
the LVDS speed is well above your target.

If you want multiple TX, to always OR to HI,then you prebias the
Lines to LO, and only source current.

CAN bus does the same, but might struggle to get to 4MHz, but ISTR
some mention of faster CAN systems - Maxim have CAN devices to 2Mbd ?

For TX, you can use CMOS+resistors to emulate current drive, or
LVDS Txmit with diodes.

The key is LVDS allows lower swings which is lower power/faster
operation.

m...@gmail.com wrote:

> I plan to use open collector gates on a serial bus on backplane for
> communication between cards. Bus access is some sort of TDMA. What is
> the maximum speed that I can go for, assuming there is only one pullup
> ? Also, which technology would be better - LS, HC or something else. I
> feel the rise time limitation would be due to pull up and the gate
> capacitance. Please comment.

Be aware that when using open-collector drivers on a common bus, there can 
be glitches that occur whenever the bus is released (the driver is 
turned-off). This is caused by current flowing through an inductor between 
the open-collector driver and the pull-up resistor(s).

You might be better off using 3-state drivers. You would have to work out 
the TDMA protocol to prevent contention but is shouldn't be hard.

Noel

Differential will give you better noise immunity.
Check out the traditional way of doing this: RS485.

Intersil have a number of very high speed RS485 drivers. ISL8487,
ISL8488 and ISL8488 can all do 5 Mbits/sec. Then there's the ISL83491
at 10 Mbits/sec and even a ISL81486 capable of a blistering 30
Mbits/sec.

Of course, RS485 is also the traditional way of doing multi-drop serial
busses - exactly what you are implementing. Check the maximum number of
nodes the chips support. Traditionally the maximum number supported by
RS485 is 16 nodes on the bus. But lately I've seen trancievers
supporting up to 128 nodes.