Hi,

I am a mature student will be doing some complex VHDL and Verilog design 
work for my course. As well as having to create and test the 
functionality of the design (in both languages) I want to document how 
the design is put together and it's complex hierarchy.

Is there anything out there that will allow me to represent my design in 
some sort of hierarchical functional blocks to use as a documentation 
tool? As I want to use both languages for the design something that 
ideally can accommodate VHDL and Verilog.

I am happy using my normal editing system for the code design so I don't 
want a 'block-to-code' type of system.

Thanks for your help.

James.

jamesp wrote:
> Hi,
> 
> I am a mature student will be doing some complex VHDL and Verilog design 
> work for my course. As well as having to create and test the 
> functionality of the design (in both languages) I want to document how 
> the design is put together and it's complex hierarchy.
> 
> Is there anything out there that will allow me to represent my design in 
> some sort of hierarchical functional blocks to use as a documentation 
> tool? As I want to use both languages for the design something that 
> ideally can accommodate VHDL and Verilog.
> 
> I am happy using my normal editing system for the code design so I don't 
> want a 'block-to-code' type of system.
> 
> Thanks for your help.
> 
> James.
Hi James,

We have a tool which we believe will address your questions. There is a 
15 day fully functional evaluation download available on the web site so 
please feel free to try it out.

www.expressivesystems.com


-- 

Cheers
Brian
___________________________________
Expressive Systems.
         www.expressivesystems.com

You can use Metor Graphics's FPGA Advantage. When I was a student I
used it to design complex VHDL designs.
You have graphical entry of HDL code. The HDL code can also be
converted to a graphical representation. See www.mentor.com for more
infos on theyr products.

A+
Mehdi