Hi,

What could be the best method to achieve zero latency context switch
between
two processes ?

Thx in advans,
Karthik Balaguru

On 2008-05-14, karthikbalaguru <k...@gmail.com> wrote:
>
> What could be the best method to achieve zero latency context switch
> between
> two processes ?

Two processors, running each process in parallel.  There's _always_
some latency when performing a context switch.  The absolute minimum
would be a single clock cycle but that isn't instantaneous.
Interrupts aren't instant for this very reason.

So, time to modify the question.  What's the maximum latency that
would be acceptable?  You can work backwards from that.

-- 
Andrew Smallshaw
a...@sdf.lonestar.org

Ammiravo la mia cresta allo specchio quando karthikbalaguru 
<k...@gmail.com> ha detto :

> Hi,
> 
> What could be the best method to achieve zero latency context switch
> between
> two processes ?
> 

As Andrew Smallshaw just said it's not possible to have zero latency in a 
context switch. The best option at all would be to have more than a group 
of registers so that all you have to do is to "point" the CPU to the one 
you want to use with no need of moving data from regs to memory and 
viceversa.


-- 
Nuno on zx-6r '04 & CR 250 '98 working in progress...
Say you, say me...say 'na mignotta!
*** www.gladio.org ***

On May 14, 4:36 pm, karthikbalaguru <karthikbalagur...@gmail.com>
wrote:
> Hi,
>
> What could be the best method to achieve zero latency context switch
> between
> two processes ?
>
> Thx in advans,
> Karthik Balaguru


Dual processors, dual RAM banks, Dual peripherals.

  Ed

On Wed, 14 May 2008 21:10:43 GMT, N1 <i...@me.it> wrote:

>Ammiravo la mia cresta allo specchio quando karthikbalaguru 
><k...@gmail.com> ha detto :
>
>> Hi,
>> 
>> What could be the best method to achieve zero latency context switch
>> between
>> two processes ?
>> 
>
>As Andrew Smallshaw just said it's not possible to have zero latency in a 
>context switch. The best option at all would be to have more than a group 
>of registers so that all you have to do is to "point" the CPU to the one 
>you want to use with no need of moving data from regs to memory and 
>viceversa.

This was exactly how it was done in the Texas TMS9900 processor with
the register set in RAM. Unfortunately this was done in an era, when
microprocessors did not have a fast cache, so the penalty during
normal operation was severe, but the context switch was fast :-).

Paul

Paul Keinanen wrote:
> N1 <i...@me.it> wrote:
>> <k...@gmail.com> ha detto :
>>
>>> What could be the best method to achieve zero latency context
>>> switch between two processes ?
>>
>> As Andrew Smallshaw just said it's not possible to have zero
>> latency in a context switch. The best option at all would be to
>> have more than a group of registers so that all you have to do
>> is to "point" the CPU to the one you want to use with no need of
>> moving data from regs to memory and viceversa.
> 
> This was exactly how it was done in the Texas TMS9900 processor
> with the register set in RAM. Unfortunately this was done in an
> era, when microprocessors did not have a fast cache, so the
> penalty during normal operation was severe, but the context
> switch was fast :-).

Remember the Z80?  One instruction flipped you to the alternate
register set (ABCDEHL).  IX, IY, SP and PC were unchanged.  You had
to be sure no idiot used the alternates in the bios, however.

-- 
 [mail]: Chuck F (cbfalconer at maineline dot net) 
 [page]: <http://cbfalconer.home.att.net>;
            Try the download section.


** Posted from http://www.teranews.com **

"CBFalconer" <c...@yahoo.com> wrote in message 
news:4...@yahoo.com...
> Remember the Z80?  One instruction flipped you to the
> alternate register set (ABCDEHL).

Two instructions.

08  EX AF,AF'   ; AF <-> AF'
D9  EXX            ; BC/DE/HL <-> BC'/DE'/HL'

    - Bill

karthikbalaguru wrote:

> What could be the best method to achieve zero latency context switch
> between two processes ?

As you can see from the other answers, this depends largely on the CPU you
are using. One exception is a simple Forth system, e.g. a threaded code
implementation ( http://www.complang.tuwien.ac.at/forth/threaded-code.html
). Instead of using interrupts, which can have large latencies because of
instruction cache flush etc., you could simply execute 100 instructions for
each process. Process switching could be done by loading a new instruction
pointer for the threaded code and stack pointer. This will be fast on every
CPU.

-- 
Frank Buss, f...@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

On Thu, 15 May 2008 00:44:44 -0400, CBFalconer <c...@yahoo.com>
wrote:

>Paul Keinanen wrote:
>> N1 <i...@me.it> wrote:
>>> <k...@gmail.com> ha detto :
>>>
>>>> What could be the best method to achieve zero latency context
>>>> switch between two processes ?
>>>
>>> As Andrew Smallshaw just said it's not possible to have zero
>>> latency in a context switch. The best option at all would be to
>>> have more than a group of registers so that all you have to do
>>> is to "point" the CPU to the one you want to use with no need of
>>> moving data from regs to memory and viceversa.
>> 
>> This was exactly how it was done in the Texas TMS9900 processor
>> with the register set in RAM. Unfortunately this was done in an
>> era, when microprocessors did not have a fast cache, so the
>> penalty during normal operation was severe, but the context
>> switch was fast :-).
>
>Remember the Z80?  One instruction flipped you to the alternate
>register set (ABCDEHL).  IX, IY, SP and PC were unchanged.  You had
>to be sure no idiot used the alternates in the bios, however.

Perfectly fine, if you only had some miniature system with just two
tasks :-).

Paul

In article <L...@giganews.com>,
Bill Leary <B...@msn.com> wrote:
>"CBFalconer" <c...@yahoo.com> wrote in message 
>news:4...@yahoo.com...
>> Remember the Z80?  One instruction flipped you to the
>> alternate register set (ABCDEHL).
>
>Two instructions.
>
>08  EX AF,AF'   ; AF <-> AF'
>D9  EXX            ; BC/DE/HL <-> BC'/DE'/HL'

I wonder why EX AF, AF' was made a distinct instruction?

Some ARMs (at least the ARM7TDMI, the only one I've messed with)
have partially banked/shadowed registers--- each of the six processor
modes has private copies of two registers (one is used by the
hardware to store a return address; the other is typically used as
a stack pointer) and the FIQ (fast interrupt) mode has another five
general-purpose registers that it doesn't need to save/restore.

-- 
   Wim Lewis <w...@hhhh.org>, Seattle, WA, USA. PGP keyID 27F772C1