>>Remember the Z80?  One instruction flipped you to the alternate
>>register set (ABCDEHL).  IX, IY, SP and PC were unchanged.  You had
>>to be sure no idiot used the alternates in the bios, however.
>
> Perfectly fine, if you only had some miniature system with just two
> tasks :-).

Which is why ZiLOG opted for a different approach for their Z8 
microcontroller - a register pointer, selecting one of the many working 
register groups in the vast register file (at least, not external RAM like 
in the TI's case).
Fast context switch and awkward program design :(

Stefan 

Wim Lewis wrote:

> In article <L...@giganews.com>,
> Bill Leary <B...@msn.com> wrote:
>>"CBFalconer" <c...@yahoo.com> wrote in message
>>news:4...@yahoo.com...
>>> Remember the Z80?  One instruction flipped you to the
>>> alternate register set (ABCDEHL).
>>
>>Two instructions.
>>
>>08  EX AF,AF'   ; AF <-> AF'
>>D9  EXX            ; BC/DE/HL <-> BC'/DE'/HL'
> 
> I wonder why EX AF, AF' was made a distinct instruction?

Good question.  I did use EX AF,AF' once to get an alternate accumulator,
but I can't remember what I was doing to make that seem like a win. 
Current versions of that product turned the whole alternate register set
over to the big timed interrupt that manages all the hardware polling.

        Mel.

In article <3...@i36g2000prf.googlegroups.com>,
karthikbalaguru  <k...@gmail.com> wrote:
>Hi,
>
>What could be the best method to achieve zero latency context switch
>between
>two processes ?

Run the two processes on a processor with CMT, chip-multithreading or
"hyper-threading", or on a "barrel processor".  In a single-pipe CPU, the
issue unit will be able to choose an instruction from each thread on a
cycle-by-cycle basis.  If there are multiple integer pipes, it may be able
to schedule instructions from both threads at the same time.

Some network processors (IXP2400) allowed one thread to wake-up a sleeping
thread.  The sleeping thread could then execute within just a few cycles.
-- 
/*  j...@world.std.com AB1GO */                        /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

Wim Lewis wrote:
> In article <L...@giganews.com>,
> Bill Leary <B...@msn.com> wrote:
>> "CBFalconer" <c...@yahoo.com> wrote in message 
>> news:4...@yahoo.com...
>>> Remember the Z80?  One instruction flipped you to the
>>> alternate register set (ABCDEHL).
>> Two instructions.
>>
>> 08  EX AF,AF'   ; AF <-> AF'
>> D9  EXX            ; BC/DE/HL <-> BC'/DE'/HL'
> 
> I wonder why EX AF, AF' was made a distinct instruction?
> 

The EX instructions and the alternative registers can be used for more 
than just a fast context switch.  The EX AF,AF' in particular lets you 
hold two accumulators in the air at a time.  It's about twenty years 
since I last programmed a Z80, so I can't remember any examples.

karthikbalaguru wrote:

> Hi,
> 
> What could be the best method to achieve zero latency context switch
> between
> two processes ?

By accepting some limitations, there are solutions.
As example the Sun Sparc has a huge register set of
256 registers, of which 32 each are for one process.
A context switch is as quick as swapping the base
pointer, basically one operation. The limitation,
there are only 8 processes like that. There might
be other architectures that operate like that.
I have no idea whether they developped any further.

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

David Brown wrote:
> Wim Lewis wrote:
> 
>> In article <L...@giganews.com>,
>> Bill Leary <B...@msn.com> wrote:
>>
>>> "CBFalconer" <c...@yahoo.com> wrote in message 
>>> news:4...@yahoo.com...
>>>
>>>> Remember the Z80?  One instruction flipped you to the
>>>> alternate register set (ABCDEHL).
>>>
>>> Two instructions.
>>>
>>> 08  EX AF,AF'   ; AF <-> AF'
>>> D9  EXX            ; BC/DE/HL <-> BC'/DE'/HL'
>>
>>
>> I wonder why EX AF, AF' was made a distinct instruction?
>>
> 
> The EX instructions and the alternative registers can be used for more 
> than just a fast context switch.  The EX AF,AF' in particular lets you 
> hold two accumulators in the air at a time.  It's about twenty years 
> since I last programmed a Z80, so I can't remember any examples.

What I disliked about Z80 is that there is no way to know which set of 
registers is current. BTW, the ADSP21xx and x51 provide for alternative 
sets, too.


Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

Vladimir Vassilevsky wrote:
> 
> 
> David Brown wrote:
>> Wim Lewis wrote:
>>
>>> In article <L...@giganews.com>,
>>> Bill Leary <B...@msn.com> wrote:
>>>
>>>> "CBFalconer" <c...@yahoo.com> wrote in message 
>>>> news:4...@yahoo.com...
>>>>
>>>>> Remember the Z80?  One instruction flipped you to the
>>>>> alternate register set (ABCDEHL).
>>>>
>>>> Two instructions.
>>>>
>>>> 08  EX AF,AF'   ; AF <-> AF'
>>>> D9  EXX            ; BC/DE/HL <-> BC'/DE'/HL'
>>>
>>>
>>> I wonder why EX AF, AF' was made a distinct instruction?
>>>
>>
>> The EX instructions and the alternative registers can be used for more 
>> than just a fast context switch.  The EX AF,AF' in particular lets you 
>> hold two accumulators in the air at a time.  It's about twenty years 
>> since I last programmed a Z80, so I can't remember any examples.
> 
> What I disliked about Z80 is that there is no way to know which set of 
> registers is current. BTW, the ADSP21xx and x51 provide for alternative 
> sets, too.

The x51 has four register banks, however only one accumulator and only 
one Xmem pointer register.

Make doing any kind of math a real pain.

> 
> 
> Vladimir Vassilevsky
> DSP and Mixed Signal Design Consultant
> http://www.abvolt.com
> 

On May 15, 8:30=EF=BF=BDpm, "Stefan Carter" <scarte...@hotmail.com> wrote:
> >>Remember the Z80? =EF=BF=BDOne instruction flipped you to the alternate
> >>register set (ABCDEHL). =EF=BF=BDIX, IY, SP and PC were unchanged. =EF=
=BF=BDYou had
> >>to be sure no idiot used the alternates in the bios, however.
>
> > Perfectly fine, if you only had some miniature system with just two
> > tasks :-).
>
> Which is why ZiLOG opted for a different approach for their Z8
> microcontroller - a register pointer,

Isn't that the same as TI?

 selecting one of the many working
> register groups in the vast register file (at least, not external RAM like=

> in the TI's case).

Some of the 9900  series had internal ram.

Many micro families have multiple register banks

> Fast context switch and awkward program design :(

Certainly not very C friendly.

>
> Stefan

Vladimir Vassilevsky wrote:
> 
> 
> David Brown wrote:
>> Wim Lewis wrote:
>>
>>> In article <L...@giganews.com>,
>>> Bill Leary <B...@msn.com> wrote:
>>>
>>>> "CBFalconer" <c...@yahoo.com> wrote in message 
>>>> news:4...@yahoo.com...
>>>>
>>>>> Remember the Z80?  One instruction flipped you to the
>>>>> alternate register set (ABCDEHL).
>>>>
>>>> Two instructions.
>>>>
>>>> 08  EX AF,AF'   ; AF <-> AF'
>>>> D9  EXX            ; BC/DE/HL <-> BC'/DE'/HL'
>>>
>>>
>>> I wonder why EX AF, AF' was made a distinct instruction?
>>>
>>
>> The EX instructions and the alternative registers can be used for more 
>> than just a fast context switch.  The EX AF,AF' in particular lets you 
>> hold two accumulators in the air at a time.  It's about twenty years 
>> since I last programmed a Z80, so I can't remember any examples.
> 
> What I disliked about Z80 is that there is no way to know which set of 
> registers is current. BTW, the ADSP21xx and x51 provide for alternative 
> sets, too.
> 

The easiest way to think about it is to assume AF, BC, DE, and HL are 
always current.  Don't try to think that you've swapped over to AF' or 
BC', DE' and HL'.  Instead, think of the EXX instruction as swapping the 
values between the real registers and the alternative registers.

>> Which is why ZiLOG opted for a different approach for their Z8
>> microcontroller - a register pointer,

>Isn't that the same as TI?

In the Z8/eZ8, all registers are/were accumulators - how did the TI handle 
this?