BobW wrote:
> "Talal Itani" <t...@verizon.net> wrote in message 
> news:suk7k.3904$JL.2049@trnddc05...
>>> To be honest 50uH and 0.1uF is a recipe for disaster. At the most a 
>>> ferrite SMT-bead should be used but usually I don't even do that. A nice 
>>> full ground plane and a nice full VCC plane is usually best. Problem with 
>>> DSP like this is that you need an additional lower voltage supply so now 
>>> you are up to three supply planes, meaning you won't get away with less 
>>> than a 6-layer board.
>>>
>>> If it's super critical you could have the analog supplies come from a 
>>> separate regulator but often converters on a chip with fast digital 
>>> processing going on are quite disappointing. A bond wire affords only so 
>>> much in RF conductivity.
>>>
>>> Hint: Carefully read up on power supply sequencing. Best case wriobng 
>>> sequencing leads to a locked up DSP, worst case to a dead DSP.
>>>
>>> Oh, and please don't top post.
>>>
>> This DSP has 3.3V and 1.8V supply voltages.  Can the same plane have both 
>> voltages?
> 
> Talal,
> 
> You really need some consulting help if you're asking questions like this. 
> The edge rates of your signals are likely to be very fast, and this requires 
> some real know-how when it comes to designing the circuitry, clock 
> distribution and trace lengths, and the general pcb layout. The previous 
> comment regarding supply sequencing should be heeded, too.
> 
> A short answer for you is this:
> 
> If you can arrange it, the controlled-impedance traces should couple to (be 
> adjacent to) solid (unsplit) GND plane layers. Then, you can split your 
> supply planes as you need. Otherwise, you have to be very careful in routing 
> your traces so as to avoid coupling gaps which will result in large 
> high-inductance coupling loops, or add extra decoupling to couple these 
> split planes near their splits.
> 
> You should seek some professional help for your design and/or take a class 
> in high-speed signal integrity.
> 

I'd agree. Best to get some help now, not after there are problems with 
the design, the boss is becoming impatient and it's almost too late. 
Talal, get a consultant that is somewhat local or pay him/her to come to 
your work place. Then you can learn the main tricks via a coaching process.

Yes, it'll cost money but it is money well spent.

-- 
Regards, Joerg

http://www.analogconsultants.com/

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Tim Wescott wrote:
> Joerg wrote:
>> Talal Itani wrote:
>>> Ok, maybe not tiny.  I have never seen this before, so I wonder whey 
>>> these inductors are there.
>>>
>>
>> Possibly a very young guy did the design. There are people who take a 
>> sledgehammer to hang a picture. Sometimes the sledgehammer then makes 
>> a hole in the wall ;-)
>>
>>>
>>>> BTW, 50uH isn't really "tiny". 
>>>
>>
>> For RF it's huge. Like a sledgehammer. Sledgehammers can cause a lot 
>> of grief.
>>
> WHAT?  You mean that semiconductor companies hire kids with no real 
> experience fresh out of college to be applications engineers?
> 
> Now THAT would imply that they look at their applications engineers as a 
> marketing expense, not a profit center.
> 

Well, suffice it to mention one episode: Just after receiving my degree 
I met a guy at an airport. Recognized him right away because we happened 
to pick up our degrees around the same time. "Hey, what are you doing 
now?" ... "Writing application notes for XYZ Corporation". <gasp>

-- 
Regards, Joerg

http://www.analogconsultants.com/

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On Sat, 21 Jun 2008 22:05:32 -0700, "BobW"
<n...@roadrunner.com> wrote:

>You should seek some professional help for your design and/or take a class 
>in high-speed signal integrity.

   At the very minimum, get this book, and pay for the fastest
shipping so you can hurry and get started reading it:
High Speed Digital Design: A Handbook of Black Magic
http://www.amazon.com/High-Speed-Digital-Design-Semiconductor/dp/0133957241
   Much of this book is about board layout, and exactly this sort of
thing.

>
>Bob

On Jun 22, 9:03 am, Guy Macon <http://www.guymacon.com/>; wrote:
> John Larkin wrote:
> >Inductors don't generally help digital chips, and may actually reduce
> >timing margins. We do use ferrite bead+capacitor filters on the supply
> >rails of some fast opamps and adc's, to keep switcher noise and
> >other-channel crosstalk from sneaking in.
>
> >The best way to power big digital chips is with solid power planes,
> >reasonably bypassed. That will present lower rail impedances than you
> >could get by isolating the bypass caps on a per-pin basis.
>
> Unless my design is cost sensitive, I generally put ferrite beads
> on the wires coming from the power supply.  I have never had this
> actually change how well anything works, but I can see a bit less
> noise with a scope, and doing it that way is fairly cheap.  I have
> seen all sorts of schemes for power/ground, but I have never seen
> any thing that beats a solid ground plane and good physical placement
> of sensitive / noise-producing sections.

I am curious about this.  I can see the theory behind adding
inductance to individual branches of the supply to prevent noise from
one section from reaching other section of the board.  But to add
inductance to the common supply line seems like it would only make
things worse.  The noise you saw a reduction in, was it from the
supply rather than from the board?

Rick

If you are going to layout the board yourself, then you need to learn
good board design techniques.  Even if you let someone else layout the
board, you should be the one telling them what to do, not the other
way around.  To do otherwise can result in a board that does not work
because of power decoupling and SI issues.

The inductors on this design are pretty bizarre and are likely not
even used on the real board.  A 50 uH inductor is rather large and
using 15 of them would stick out like a sore thumb.  I expect they
were replaced in production with 0 ohm jumpers.  In general, inductors
are not needed for power supplies.  Good ground planes do an excellent
job of minimizing high frequency noise.  Low frequency noise is
another issue however.  I used a CP Clare part once that had 0 dB
PSRR.  They didn't put that in the data sheet, they let you figure it
out on your own.  My analog power rail was derived from the digital
power rail and had 10 mV of 300 Hz noise from a control loop in the
DSP.  The 10 mV of noise coupled directly onto the phone line and
showed up as a low level, but very distinct hum or buzz.

0 dB of PSRR is unusual in a chip of any sort (I have to take my hat
off to CP Clare).  But the point is that you need to include the right
capacitance to handle noise at all frequencies.  By preventing the
noise in the first place, you don't have to worry about it coupling
into other circuits.

Rick

Rick

On Jun 21, 7:43 pm, "Talal Itani" <tit...@verizon.net> wrote:
> What if we are not sensible about the layout?  Meaning, I layout the board
> myself.
>
> >> The DSP is a TI F2808.  The schematics I was referring to are here
> >>http://www.ti.com/litv/zip/sprr098.  It is a zip file.  Once you unzip
> >> the file, 2 pdf files appear.  The larger file has the schematics I am
> >> referring to.  The inductors are at the top-left corner of the screen.
>
> > This mediocre design is obviously made by a superstitious and
> > unexperienced person. There are several things in the schematics that
> > should be done differently. No wonder that at some time ago the designer
> > had burned with the EMC, and after that he sticks the inductors
> > everywhere. The value of 50uH is ridiculous. Never mind those inductors;
> > with the sensible layout the F28xx doesn't need them.
>
> > Vladimir Vassilevsky
> > DSP and Mixed Signal Design Consultant
> >http://www.abvolt.com

John Larkin wrote:
> On Sun, 22 Jun 2008 13:03:09 +0000, Guy Macon
> <http://www.guymacon.com/>; wrote:
> 
>>
>>
>> John Larkin wrote:
>>
>>> Inductors don't generally help digital chips, and may actually reduce
>>> timing margins. We do use ferrite bead+capacitor filters on the supply
>>> rails of some fast opamps and adc's, to keep switcher noise and
>>> other-channel crosstalk from sneaking in.
>>>
>>> The best way to power big digital chips is with solid power planes,
>>> reasonably bypassed. That will present lower rail impedances than you
>>> could get by isolating the bypass caps on a per-pin basis.
>> Unless my design is cost sensitive, I generally put ferrite beads
>> on the wires coming from the power supply.  I have never had this 
>> actually change how well anything works, but I can see a bit less 
>> noise with a scope, and doing it that way is fairly cheap.  I have
>> seen all sorts of schemes for power/ground, but I have never seen 
>> any thing that beats a solid ground plane and good physical placement
>> of sensitive / noise-producing sections.
> 
> Any time you add inductance to a supply rail, the consequences should
> be analyzed. It could...
> 
> Series resonate at some switching supply frequency and *increase*
> downstream ripple
> 
> Add DC drop. With chip core voltages below 1 volt, and timing margins
> critical, that could get interesting
> 
> If a chip can grossly shift its average current needs (like a uP, or
> some analog driver) the added L can make the supply dip.
> 

Or spike. Old rule with inductors: They want to maintain their current 
no matter what. If they can't then they do what taxing authorities do 
when they run out of dough: Raise the voltage ...


> The inductor could fry!
> 
> 
> I've seen all of these.
> 

Seen some grief in that domain as well. Including freaking expensive 
FPGA that have become doorstops.

-- 
Regards, Joerg

http://www.analogconsultants.com/

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Paul Keinanen wrote:
> On Sat, 21 Jun 2008 15:25:38 -0700 (PDT), b...@ieee.org wrote:
> 
>> On Jun 22, 5:52 am, Paul Keinanen <keina...@sci.fi> wrote:
> 
>>> Are you sure that these are ordinary inductors or just a wire through
>>> a ferrite bead?
>>>
>>> While the ferrite will increase the inductance, a suitable ferrite
>>> material is also quite lossy at higher frequencies, reducing the risk
>>> for unwanted resonances with the capacitors.
>> Sadly, you can't rely on this. I've had to put little resistors in
>> series with ferrite bead to kill a resonance - admittedly at a few
>> hundred kHz, where the bead doesn't look that lossy.
> 
> It would be quite hard to find material that would be lossy at such
> low frequencies. For instance materials listed at
> http://www.fair-rite.com/newfair/materials.htm start at 1 MHz
> (material 31), while the common material 73 have significant losses
> only above 10 MHz.
> 

I am lossy at low frequencies. Met my wife at an ultrasound company and 
she was quited stunned that my body would absorb even 3.5MHz to the 
point where she couldn't get a decent ultrasound image. Never seen it 
this bad before. She married me anyway.

-- 
Regards, Joerg

http://www.analogconsultants.com/

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"Ben Bradley" <b...@etcmail.com> wrote in message 
news:9...@4ax.com...
> On Sat, 21 Jun 2008 22:05:32 -0700, "BobW"
> <n...@roadrunner.com> wrote:
>
>>You should seek some professional help for your design and/or take a class
>>in high-speed signal integrity.
>
>   At the very minimum, get this book, and pay for the fastest
> shipping so you can hurry and get started reading it:
> High Speed Digital Design: A Handbook of Black Magic
> http://www.amazon.com/High-Speed-Digital-Design-Semiconductor/dp/0133957241
>   Much of this book is about board layout, and exactly this sort of
> thing.
>
>>
>>Bob
>

I've found that the HoJo book is great for a reference, but find it too 
jumbled to be a coherent teaching tool. It's certainly a good place to 
start.

When I've seen Dr. Johnson in action (e.g. on some Xilinx webcasts) he's a 
very good teacher.

Bob
-- 
== NOTE: I automatically delete all Google Group posts due to uncontrolled 
SPAM == 

All of us old geezers know that there is a tiny inductor in series with 
every bypass cap.  Impossible to get away without it.  The trick is to 
minimize it.

Jim

-- 
"It is the mark of an educated mind to be able to entertain a thought 
without accepting it."
        --Aristotle 

Tim Wescott wrote:

>>
> WHAT?  You mean that semiconductor companies hire kids with no real 
> experience fresh out of college to be applications engineers?

Don't you know? Those who can't be the real engineers take the position 
of the application engineers.

> Now THAT would imply that they look at their applications engineers as a 
> marketing expense, not a profit center.

Of course they are. Application engoneer is a sales position.


Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com