"Vladimir Vassilevsky" <a...@hotmail.com> wrote in message 
news:8vA7k.5248$L_.3...@flpi150.ffdc.sbc.com...
>
>
> MK wrote:
>
>> I designed a board with an 'F2808 about 2 years ago.  Based on TI app 
>> notes I
>> put 100nH in series with the two ADC power pins only and 2uF to ground on 
>> each (2 * 0603 caps - different values).
>>
>> Was it necessary - I don't know - never tried it without.
>>
>> Did the ADC work - yes - I was impressed at how well it worked.
>
> The internal ADC of TI 28xx is crap. It has tremendously inacurate 
> internal reference and high zero offset. With 12 bits available, the true 
> accuracy is about 8 bits unless you have the ADC calibrated.
>
>> The board was 4 layers with careful design of gorund planes/fills around 
>> the processor and decoupling caps on both sides.
>
> There is no need for 4 layer board with 28xx. The layout can be done on 
> two layers just fine. Been there, done that.
>
>
> Vladimir Vassilevsky
> DSP and Mixed Signal Design Consultant
> http://www.abvolt.com

Hello Vlad,

We were able to arrange for calibration of the ADC on board and could easily 
deal with the offset issues.

We went 4 layer because we wanted it to work first time, 6M samples/sec and 
reasonable ADC performance for an on chip quite fast ADC.

It worked and was delivered on time and to spec.

Sure we could have got it on 2 layers, delivered it late, not quite working 
and saved a few £ on the board.

Did you never hear of "good, cheap, quick - pick any two" ?

Michael Kellett

On Mon, 23 Jun 2008 13:14:57 +1200, Terry Given <m...@ieee.org>
wrote:

>Tim Wescott wrote:
>> Joerg wrote:
>> 
>>> Tim Wescott wrote:
>>>
>>>> Talal Itani wrote:
>>>>
>>>>> Hello,
>>>>>
>>>>> I was looking at the schematics for a DSP-based board, running at 
>>>>> 100 MHz. They have a tiny inductor with every bypass cap around the 
>>>>> DSP.  Do you think this is necessary?  This DSP has analog stuff 
>>>>> built-in.  If we do not need analog, can the inductors be eliminated?
>>>>>
>>>>> Thanks,
>>>>> T.I.
>>>>>
>>>> Search for newsgroup postings with "Jeorg" and "ground" or 
>>>> "grounding" in them.
>>>>
>>>> You'll get a load of (AFAIK) good opinions.
>>>>
>>>
>>> Thanks for the kudos. It would have to be "Joerg" though. Sometimes I 
>>> wish I had an easier name.
>>>
>> 'O' before 'E' unless I'm at sea?
>> 
>> Dunno why I can't keep it straight.
>> 
>>>
>>>> Inductors in series with the caps would tend to isolate the power 
>>>> supply from noise in the DSP, but it would also create a bunch of odd 
>>>> resonances.  It's not how I'd want to isolate a power supply from a 
>>>> chip.
>>>>
>>>
>>> It will become really interesting when the DSP exhibits a somewhat 
>>> burst-like load behavior. On the scope it'll look like Dolphins 
>>> frolicking in the ocean.
>>>
>> That's kinda what I thought.  Plus I see no reason to do each power line 
>> individually, and some good reasons not to (Different versions of VDD at 
>> different points in the circuit, oh boy!).
>> 
>
>they are also probably ferrite beads, rather than inductors per se. but 
>I have corrected a few designs where the "engineers" really did use 
>inductors. nasty little bobbin core things. yuk!
>
>I've seen quite a few app notes with FBs liberally sprinkled everywhere. 
>I presume this is because its easier than thinking. that being said, I 
>have a design thats soon to undergo EMC testing where I have exactly 
>followed the manufacturers recommendations for the FPGA & HY ships, but 
>I plan on muntzing most of the FBs during a day at the EMC lab. odds on 
>I can leave ALL of them off...
>
>Cheers
>Terry

Mad man Muntz must be spinning in his grave.
   

"MK" <n...@please.com> wrote in message
news:p...@bt.com...
>
> "Vladimir Vassilevsky" <a...@hotmail.com> wrote in message
> news:8vA7k.5248$L_.3...@flpi150.ffdc.sbc.com...
> >
> >
> > MK wrote:
> >
> >> I designed a board with an 'F2808 about 2 years ago.  Based on TI app
> >> notes I
> >> put 100nH in series with the two ADC power pins only and 2uF to ground
on
> >> each (2 * 0603 caps - different values).
> >>
> >> Was it necessary - I don't know - never tried it without.
> >>
> >> Did the ADC work - yes - I was impressed at how well it worked.
> >
> > The internal ADC of TI 28xx is crap. It has tremendously inacurate
> > internal reference and high zero offset. With 12 bits available, the
true
> > accuracy is about 8 bits unless you have the ADC calibrated.
> >
> >> The board was 4 layers with careful design of gorund planes/fills
around
> >> the processor and decoupling caps on both sides.
> >
> > There is no need for 4 layer board with 28xx. The layout can be done on
> > two layers just fine. Been there, done that.
> >
>
> We were able to arrange for calibration of the ADC on board and could
easily
> deal with the offset issues.
>
> We went 4 layer because we wanted it to work first time, 6M samples/sec
and
> reasonable ADC performance for an on chip quite fast ADC.
> It worked and was delivered on time and to spec.

> Sure we could have got it on 2 layers, delivered it late, not quite
working
> and saved a few £ on the board.
>
> Did you never hear of "good, cheap, quick - pick any two" ?
>

We develop the consumer applications where every $ matters. Two vs four
layer PCB is a big difference in the cost, so I don't use the multilayer
boards unless it is really required. Despite of the popular beliefs, many
analog or digital designs can be built in two layers just fine. It takes
care, understanding and attention to details.

I averaged several sequential conversions of the 28xx ADC to get better
noise performance, so I traded the speed for the SNR. It worked like
expected for the noise however the problem was the beat tones between the
ADC clock and the peripheral clock. Had to optimize the division ratios. The
ADC manual is pretty vague (as it is usual with TI), so it is not clear what
is the exact position of the sampling instants of the sequencer, and how the
whole thing works. What set me off is that there are two similar but not
quite the same sequencers there. Another stupid thing is that the ADC range
is 0...3V absolute, not 0...3.3V ratiometric. So the 3.3V can't be used as
the reference for the level shifting, etc. unless the 3.3V is measured
against the internal reference.


Vladimir Vassilevsky
DSP and Mixed Signal Consultant
www.abvolt.com

"Vladimir Vassilevsky" <a...@hotmail.com> wrote in message 
news:IoA7k.6348$N...@nlpi068.nbdc.sbc.com...
> Don't you know? Those who can't be the real engineers take the position of 
> the application engineers.

Much of the time that's probably so, but not always -- I know a guy who's a 
decent engineer, having run his own successful (profitable) company for 
awhile, working as a consultant, etc., before deciding to become an FAE once 
he got somewhat older and just wanted to settle down a bit and spend more time 
with his wife and kids.  I can definitely see some of the attraction... you 
get to work on a much wider variety of projects than most regular engineers 
ever would, yet the stress level is probably much lower than those engineers 
who are facing tight deadlines and still have many unsolved problem.  Indeed, 
a good FAE can really relieve a lot of that stress by providing real, working 
solutions to their needs.

Personally I'm suspect of anyone claiming to be an FAE who doesn't actually 
have access to (or chooses not to use) a workbench, test equipment, and 
whatever else they ought to have to be able to adequately build and test the 
circuits/ICs/whatever they're recommending.  Unfortunately, this does seem to 
be a rather large percentage of all FAEs.

Hi Vladimar,

"Vladimir Vassilevsky" <a...@hotmail.com> wrote in message 
news:d5M7k.6300$c...@nlpi064.nbdc.sbc.com...
> Despite of the popular beliefs, many
> analog or digital designs can be built in two layers just fine. It takes
> care, understanding and attention to details.

For many companies, coming up with that "care, understanding, and attention to 
detail" requires both significant time and often money -- so I think MK's 
point is valid, since those are not always available!

But I think that all of us would be interested to hear your advice on 
designing high-speed/low-noise circuitry on two-layer PCBs; it's not the sort 
of material that's commonly discussed.

Do you recommend any microcontrollers or DSPs with decent references on-board? 
We use a number of Atmel AVR microcontrollers and most often it's with an 
external reference, as the internal one is pretty bad; about +/-10% (!). 
Being charitable, I want to believe that you just can't build a reference 
that's much better using whatever process they have available to them, but 
perhaps it is just a lack of better circuit designers (e.g., someone like Jim 
could easily build them 1% references using the same process).

---Joel

Terry Given wrote:
> Joerg wrote:
>> John Larkin wrote:
>>
>>> On Sun, 22 Jun 2008 13:03:09 +0000, Guy Macon
>>> <http://www.guymacon.com/>; wrote:
>>>
>>>>
>>>>
>>>> John Larkin wrote:
>>>>
>>>>> Inductors don't generally help digital chips, and may actually reduce
>>>>> timing margins. We do use ferrite bead+capacitor filters on the supply
>>>>> rails of some fast opamps and adc's, to keep switcher noise and
>>>>> other-channel crosstalk from sneaking in.
>>>>>
>>>>> The best way to power big digital chips is with solid power planes,
>>>>> reasonably bypassed. That will present lower rail impedances than you
>>>>> could get by isolating the bypass caps on a per-pin basis.
>>>>
>>>> Unless my design is cost sensitive, I generally put ferrite beads
>>>> on the wires coming from the power supply.  I have never had this 
>>>> actually change how well anything works, but I can see a bit less 
>>>> noise with a scope, and doing it that way is fairly cheap.  I have
>>>> seen all sorts of schemes for power/ground, but I have never seen 
>>>> any thing that beats a solid ground plane and good physical placement
>>>> of sensitive / noise-producing sections.
>>>
>>>
>>> Any time you add inductance to a supply rail, the consequences should
>>> be analyzed. It could...
>>>
>>> Series resonate at some switching supply frequency and *increase*
>>> downstream ripple
>>>
>>> Add DC drop. With chip core voltages below 1 volt, and timing margins
>>> critical, that could get interesting
>>>
>>> If a chip can grossly shift its average current needs (like a uP, or
>>> some analog driver) the added L can make the supply dip.
>>>
>>
>> Or spike. Old rule with inductors: They want to maintain their current 
>> no matter what. If they can't then they do what taxing authorities do 
>> when they run out of dough: Raise the voltage ...
>>
>>
>>> The inductor could fry!
>>>
>>>
>>> I've seen all of these.
>>>
>>
>> Seen some grief in that domain as well. Including freaking expensive 
>> FPGA that have become doorstops.
>>
> 
> One design I looked at used a 600MHz agilent parallel/serial - 
> serail/parallel chipset. there was a 1uH inductor between the 0V plane 
> of the receiver/equaliser chip & the agilent serial/parallel chip 0V plane.
> 
> oddly enough the serial link seemed a bit flaky. that didnt stop the 
> company from selling hundreds of millions of dollars worth of product, 
> but it did meant they could daisy chain 2 units, rather than the dozens 
> they planned on.
> 
> and there was no way I could convince their head of engineering this was 
> a bad thing. OTOH they paid my bill, and I did fix a whole host of other 
> problems.
> 


Shhht! You are taking away a chunk of my source of income :-)

-- 
Regards, Joerg

http://www.analogconsultants.com/

"gmail" domain blocked because of excessive spam.
Use another domain or send PM.

Terry Given wrote:
> Tim Wescott wrote:
>> Joerg wrote:
>>
>>> Tim Wescott wrote:
>>>
>>>> Talal Itani wrote:
>>>>
>>>>> Hello,
>>>>>
>>>>> I was looking at the schematics for a DSP-based board, running at 
>>>>> 100 MHz. They have a tiny inductor with every bypass cap around the 
>>>>> DSP.  Do you think this is necessary?  This DSP has analog stuff 
>>>>> built-in.  If we do not need analog, can the inductors be eliminated?
>>>>>
>>>>> Thanks,
>>>>> T.I.
>>>>>
>>>> Search for newsgroup postings with "Jeorg" and "ground" or 
>>>> "grounding" in them.
>>>>
>>>> You'll get a load of (AFAIK) good opinions.
>>>>
>>>
>>> Thanks for the kudos. It would have to be "Joerg" though. Sometimes I 
>>> wish I had an easier name.
>>>
>> 'O' before 'E' unless I'm at sea?
>>
>> Dunno why I can't keep it straight.
>>
>>>
>>>> Inductors in series with the caps would tend to isolate the power 
>>>> supply from noise in the DSP, but it would also create a bunch of 
>>>> odd resonances.  It's not how I'd want to isolate a power supply 
>>>> from a chip.
>>>>
>>>
>>> It will become really interesting when the DSP exhibits a somewhat 
>>> burst-like load behavior. On the scope it'll look like Dolphins 
>>> frolicking in the ocean.
>>>
>> That's kinda what I thought.  Plus I see no reason to do each power 
>> line individually, and some good reasons not to (Different versions of 
>> VDD at different points in the circuit, oh boy!).
>>
> 
> they are also probably ferrite beads, rather than inductors per se. but 
> I have corrected a few designs where the "engineers" really did use 
> inductors. nasty little bobbin core things. yuk!
> 

It never fails to impress clients when changes consist of lots of parts 
being replaced with a snippet of wire.


> I've seen quite a few app notes with FBs liberally sprinkled everywhere. 
> I presume this is because its easier than thinking. that being said, I 
> have a design thats soon to undergo EMC testing where I have exactly 
> followed the manufacturers recommendations for the FPGA & HY ships, but 
> I plan on muntzing most of the FBs during a day at the EMC lab. odds on 
> I can leave ALL of them off...
> 

You had Muntz TV sets in NZ???

-- 
Regards, Joerg

http://www.analogconsultants.com/

"gmail" domain blocked because of excessive spam.
Use another domain or send PM.

Joel Koltner wrote:

> "Vladimir Vassilevsky" <a...@hotmail.com> wrote:

>>Despite of the popular beliefs, many
>>analog or digital designs can be built in two layers just fine. It takes
>>care, understanding and attention to details.
> 
> For many companies, coming up with that "care, understanding, and attention to 
> detail" requires both significant time and often money -- so I think MK's 
> point is valid, since those are not always available!

Classic question of the development cost vs production cost; it depends.

> But I think that all of us would be interested to hear your advice on 
> designing high-speed/low-noise circuitry on two-layer PCBs; it's not the sort 
> of material that's commonly discussed.

There is no magic to it; just understanding which way the current flows 
and distinguishing a ground and a signal return path.

> Do you recommend any microcontrollers or DSPs with decent references on-board? 

Analog Devices ADUCxxxx series.

> We use a number of Atmel AVR microcontrollers and most often it's with an 
> external reference, as the internal one is pretty bad; about +/-10% (!).

The good thing about AVR is that it is possible to use the external 
reference, and that the ADC input range is from 0 to Vcc. The ADC of TMS 
28xx can't do that.

> Being charitable, I want to believe that you just can't build a reference 
> that's much better using whatever process they have available to them, but 
> perhaps it is just a lack of better circuit designers (e.g., someone like Jim 
> could easily build them 1% references using the same process).

Perhaps there is a limitation of the high speed CMOS process which 
doesn't allow making reasonable on-chip ADCs. May be Jim can explain us why.

> 
> ---Joel
> 

Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

"Vladimir Vassilevsky" <a...@hotmail.com> wrote in message 
news:7kT7k.2479$L...@nlpi065.nbdc.sbc.com...
> Analog Devices ADUCxxxx series.

Thanks, I'll take a look; always interesting to see what else is out there.

> The good thing about AVR is that it is possible to use the external 
> reference, and that the ADC input range is from 0 to Vcc. The ADC of TMS 
> 28xx can't do that.

What Atmel did poorly with the AVR was allowing for a second, low-speed 
oscillator for, e.g., "sleep" mode.  They can do it, but only just barely --  
they let you run one timer off of a second clock source (such as a 32kHz 
cystal), which then wakes up the CPU to do whatever.  Workable, but nowhere 
near as robust as the TI MSP430, where some of them let you have a couple of 
clock sources (e.g., 32kHz and 16MHz or whatever), run the entire CPU off of 
either one (or the internal RC oscillator), switch between them on the fly, 
etc.

I'm told they've attempted to imprveo on this situation in their new "xMega" 
AVRs.

---Joel

Joerg wrote:
> Terry Given wrote:
> 
>> Tim Wescott wrote:
>>
>>> Joerg wrote:
>>>
>>>> Tim Wescott wrote:
>>>>
>>>>> Talal Itani wrote:
>>>>>
>>>>>> Hello,
>>>>>>
>>>>>> I was looking at the schematics for a DSP-based board, running at 
>>>>>> 100 MHz. They have a tiny inductor with every bypass cap around 
>>>>>> the DSP.  Do you think this is necessary?  This DSP has analog 
>>>>>> stuff built-in.  If we do not need analog, can the inductors be 
>>>>>> eliminated?
>>>>>>
>>>>>> Thanks,
>>>>>> T.I.
>>>>>>
>>>>> Search for newsgroup postings with "Jeorg" and "ground" or 
>>>>> "grounding" in them.
>>>>>
>>>>> You'll get a load of (AFAIK) good opinions.
>>>>>
>>>>
>>>> Thanks for the kudos. It would have to be "Joerg" though. Sometimes 
>>>> I wish I had an easier name.
>>>>
>>> 'O' before 'E' unless I'm at sea?
>>>
>>> Dunno why I can't keep it straight.
>>>
>>>>
>>>>> Inductors in series with the caps would tend to isolate the power 
>>>>> supply from noise in the DSP, but it would also create a bunch of 
>>>>> odd resonances.  It's not how I'd want to isolate a power supply 
>>>>> from a chip.
>>>>>
>>>>
>>>> It will become really interesting when the DSP exhibits a somewhat 
>>>> burst-like load behavior. On the scope it'll look like Dolphins 
>>>> frolicking in the ocean.
>>>>
>>> That's kinda what I thought.  Plus I see no reason to do each power 
>>> line individually, and some good reasons not to (Different versions 
>>> of VDD at different points in the circuit, oh boy!).
>>>
>>
>> they are also probably ferrite beads, rather than inductors per se. 
>> but I have corrected a few designs where the "engineers" really did 
>> use inductors. nasty little bobbin core things. yuk!
>>
> 
> It never fails to impress clients when changes consist of lots of parts 
> being replaced with a snippet of wire.
> 
> 
>> I've seen quite a few app notes with FBs liberally sprinkled 
>> everywhere. I presume this is because its easier than thinking. that 
>> being said, I have a design thats soon to undergo EMC testing where I 
>> have exactly followed the manufacturers recommendations for the FPGA & 
>> HY ships, but I plan on muntzing most of the FBs during a day at the 
>> EMC lab. odds on I can leave ALL of them off...
>>
> 
> You had Muntz TV sets in NZ???
> 

nope, I just read widely. and this design absolutely had to work first 
time, so I just corrected the obvious errors, and planned the muntzing 
for a 2nd spin cost-down :)


oh yeah, I too know the evil twisted wire trick.

Cheers
Terry