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Tutorials
The 2026 Embedded Online Conference

VHDL tutorial - combining clocked and sequential logic

Gene BrenimanGene Breniman March 3, 2008

Need the ADC clock to sometimes be the raw 40MHz input? Gene Breniman shows how to extend a reloadable, counter-based VHDL clock divider to support a master-clock pass-through by using a conditional signal assignment to switch between the internal ADCClk and Mclk. The article also covers remapping ClkSel values and includes a working XC2C32A CPLD build that leaves room for future enhancements.


Designing Embedded Systems with FPGA-2

Pragnesh PatelPragnesh Patel November 13, 200710 comments

Turning an FPGA hardware design into a running embedded system is mostly tool work. This post walks through using Xilinx EDK to compile a base design into a .bit bitstream, generate libraries and board support packages from .mhs and .mss files, and build MicroBlaze applications with GCC. It highlights the default boot placement at 0x0 and why some apps need an explicit execution transfer.


VHDL tutorial - part 2 - Testbench

Gene BrenimanGene Breniman October 30, 20073 comments

In this follow-up Gene Breniman builds a VHDL testbench in Xilinx ISE, showing how to generate a continuous master clock, apply a power-on reset, and sequence register strobes to change clock divisors. He walks through timing waits and observation delays needed to verify ADC clock rates. The article also shows how simulation exposed a copy-paste bug in the original design.


Designing Embedded System with FPGA - 1

Pragnesh PatelPragnesh Patel October 28, 200711 comments

Getting an embedded system running on an FPGA is much simpler than it sounds when you use Xilinx EDK and a soft processor. Pragnesh Patel walks through a beginner-friendly approach using the MicroBlaze CPU, drag-and-drop IP cores, and a Spartan-3E starter kit so you can assemble peripherals without deep VHDL knowledge. The post focuses on the EDK base system builder and first setup steps to generate a working design.


Hidden Gems from the Embedded Online Conference Archives - Part 1

Tim GuiteTim Guite March 5, 2025

Discussion of a "hidden gem" from the Embedded Online Conference archives!


Tracing code and checking timings

Richard DorfnerRichard Dorfner May 25, 20115 comments

When you cannot afford logs or to stop the CPU, GPIO toggles become a powerful real-time tracer. Richard shows how driving IO pins and watching them with an oscilloscope or logic analyzer reveals control flow, function timings, and ISR activity with very little overhead. He also explains using direct port writes and conditional compilation to keep measurements noninvasive and easy to enable or disable.


Layout recomendations and tips for best performance against EMC

Dr. Maykel AlonsoDr. Maykel Alonso January 4, 2013

Good PCB layout will prevent many EMC headaches before you even power the board. Maykel Alonso offers a practical checklist covering component and feed analysis, package and PCB choices, placement, routing, and via rules. The post focuses on concrete, low-effort measures like preferring SMD parts, using a 4-layer FR-4 stack with dedicated ground and power planes, and keeping return paths tight to cut emissions and susceptibility.


Intro to Microcontrollers Part 2: AVR Microcontrollers

 July 11, 2013

This follow-up explores getting an AVR Dragon working with an ATtiny24A, covering the necessary cables, BOM choices, and Atmel Studio setup. It walks through firmware updates, an ADC-based internal temperature sensor example using reduced-noise ADC and ISR handling, and practical debugging tips including debugWire versus ISP and high-voltage recovery. Expect candid hardware caveats like weak drive strength and 5V power quirks.


The 2026 Embedded Online Conference