First Steps in OrCAD 16 [Capture]
A practical, beginner-friendly walkthrough of OrCAD 16 Capture that gets you from a blank project to a netlist ready for PCB layout. Maykel explains the OrCAD suite, project tree and design cache behavior, how to manage part libraries, and the Tools menu utilities you should run. The article ends with step-by-step instructions for creating the .mnl netlist and previews a follow-up on layout and footprint libraries.
Using XML to describe embedded devices (and speak to them)
Make embedded devices tell you what they can do. Martin Strubel shows how to use XML and XSLT with the DClib/netpp framework to describe hardware, map registers into abstract properties, and auto-generate compact C, documentation, and VHDL. The netpp property protocol then lets you probe, query, and control those properties over TCP, UDP, or other transports, simplifying test benches and multi-device families.
Deeply embedded design example - Logic replacement
Gene Breniman shows how a tiny PIC10F200 can replace a forest of discrete timing components to control six 10A H-bridges, letting firmware tune sequencing to cut EMI and reduce cost. He walks through analyzing the original RC/inverter delays, choosing the PIC, pinout and timer setup, and implementing compact assembly firmware that reproduces and improves the timing behavior. The result is fewer parts, saved board space, and better EMI control.
VHDL tutorial - A practical example - part 3 - VHDL testbench
Gene Breniman walks a complete VHDL testbench workflow for a CPLD-based data acquisition engine, from Xilinx ISE testbench generation to stimulus processes. He shows clock and SPI gating, a simulated ADC data generator tied to ADC_LRCK and ADC_BCK, and how simulation revealed a timing bug in the nvSRAM header that was then fixed in the VHDL. Practical and hands-on for verification work.
VHDL tutorial - A practical example - part 2 - VHDL coding
Gene Breniman walks through the VHDL coding for a CPLD-based data acquisition engine, turning the hardware spec into a working state machine and signal generators. The article explains SPI and I2S timing choices, an internal SPI peripheral latch, and counter-based timing (seqCount and CycleCnt) used to create LRCK, BCK, SPI SCK and nvSRAM write control. It’s a practical, implementation-focused guide for embedded designers.
VHDL tutorial - A practical example - part 1 - Hardware
Gene Breniman walks through a practical CPLD-based data acquisition engine built for a low-power handheld instrument, focusing on hardware choices, signal flow, and pin assignments. The article explains component selection including a PCM1870 ADC, CY14B101Q2 serial nvSRAM, and an XC2C64A CPLD, and shows how the CPLD acts as an SPI sequencer and I2S clock master while minimizing microcontroller pins and power draw.
Size matters - System success depends on initial design
A seemingly small UI choice can reshape an entire embedded system. Gene Breniman uses a real product example to show how picking a graphic touchscreen instead of a character LCD can multiply CPU, memory, OS, and licensing needs. The post explains why capturing requirements early and planning for growth paths keeps complexity and cost under control, and how to size hardware to fit real needs.
Software Prototyping
Software prototypes can save a lot of pain during bring-up, and Gene Breniman argues they deserve a place in the development process. He revisits an earlier post, then points readers to Jack G. Ganssle’s article on creating software prototypes, where test code becomes the model for the real product software. It is a short but practical reminder that early code can do more than just validate hardware.
Bringing up Baby - product development thoughts
After months of defining, specifying, and designing, Gene Breniman finally reaches the first semi-functional prototypes of a new product. He walks through the practical steps that get a board from idea to bring-up, from picking parts and laying out the PCB to inspecting assemblies and verifying firmware with low-level tests. Along the way, he shares hard-earned lessons about component availability, incoming inspection, and catching mistakes early.
Deeply embedded design example - Logic replacement
Gene Breniman shows how a tiny PIC10F200 can replace a forest of discrete timing components to control six 10A H-bridges, letting firmware tune sequencing to cut EMI and reduce cost. He walks through analyzing the original RC/inverter delays, choosing the PIC, pinout and timer setup, and implementing compact assembly firmware that reproduces and improves the timing behavior. The result is fewer parts, saved board space, and better EMI control.
Make Your Own MCU Boards (2023 Teardown Conference)
Ditch the development boards! Products like the Nucleo development boards serve a wonderful purpose, but they’re ill-suited for projects that need to be small and cheap, such as hobby projects or products just beginning a production run. In this talk (a recording from the 2023 Teardown Conference), you’ll learn how to put a microcontroller or other custom circuit on a PCB a little larger than a stick of gum for less than $3 a board.
Practical protection against dust and water (i.e. IP protection)
Needing IP65 protection while exposing humidity and pressure sensors on a tight $15 budget, Dr Cagri Tanriover hunted for a practical fix. He found that an SHT2x humidity sensor with a microporous filter cap and O-ring provides IP67-level protection, and by matching a pressure sensor that fits the same cap he met and exceeded the IP65 requirement. The post shows a low-cost, component-level workaround.
Size matters - System success depends on initial design
A seemingly small UI choice can reshape an entire embedded system. Gene Breniman uses a real product example to show how picking a graphic touchscreen instead of a character LCD can multiply CPU, memory, OS, and licensing needs. The post explains why capturing requirements early and planning for growth paths keeps complexity and cost under control, and how to size hardware to fit real needs.
Layout recomendations and tips for best performance against EMC
Good PCB layout will prevent many EMC headaches before you even power the board. Maykel Alonso offers a practical checklist covering component and feed analysis, package and PCB choices, placement, routing, and via rules. The post focuses on concrete, low-effort measures like preferring SMD parts, using a 4-layer FR-4 stack with dedicated ground and power planes, and keeping return paths tight to cut emissions and susceptibility.
Software Prototyping
Software prototypes can save a lot of pain during bring-up, and Gene Breniman argues they deserve a place in the development process. He revisits an earlier post, then points readers to Jack G. Ganssle’s article on creating software prototypes, where test code becomes the model for the real product software. It is a short but practical reminder that early code can do more than just validate hardware.
Bringing up Baby - product development thoughts
After months of defining, specifying, and designing, Gene Breniman finally reaches the first semi-functional prototypes of a new product. He walks through the practical steps that get a board from idea to bring-up, from picking parts and laying out the PCB to inspecting assemblies and verifying firmware with low-level tests. Along the way, he shares hard-earned lessons about component availability, incoming inspection, and catching mistakes early.
Off the shelf availability of Custom IoT Gateway
Choosing the right gateway can make or break an IoT deployment, yet industrial gateways are often expensive and generic. This post walks through practical criteria for off-the-shelf and custom gateways, covering edge computing trade-offs, mainframe versus embedded Linux, SoC and ADC choices, interfacing and debugging needs, and when to design your own hardware for real-time or protocol demands.
Requirements, Specifications and Tests
A practical workflow keeps embedded projects predictable and reduces late surprises. Start with a client-driven Set of Requirements, then derive a QA Test Set from those requirements, and write a Technical Spec that maps to the design. The method enforces change control, helps catch feature creep early, and makes final acceptance straightforward for non-engineer testers.
Software is free and can right any wrong
Software changes are so much easier than hardware modifications, so the temptation is always to take this approach to fixing bugs. This may not always be a good idea.
Off the shelf availability of Custom IoT Gateway
Choosing the right gateway can make or break an IoT deployment, yet industrial gateways are often expensive and generic. This post walks through practical criteria for off-the-shelf and custom gateways, covering edge computing trade-offs, mainframe versus embedded Linux, SoC and ADC choices, interfacing and debugging needs, and when to design your own hardware for real-time or protocol demands.
Optimizing Hardware Design: Reducing Iterations with DSM
Often, product teams curate feature roadmaps that fail to account for the interdependencies in product components. For this article, I wrote about how system architecture tools like Design(dependency) Structure matrix (DSM) can be used to evaluate feature roadmaps to avoid the purgatory of change propagation and accompanying endless Iteration loops. These iteration loops are sometimes affordable (manageable) in software development (Agile saves lives), but for hardware teams - especially small product teams and startups - the lost time, and money is the stuff of which product graves are made.
Project Log: Pixelblaze Christmas Lights
Festive fun and the hacker spirit combine in my janky attempt to adorn my house with addressable LEDs! In this post, I show you how I used a Pixelblaze and a cheap strip of WS2811 RGB LEDs (and not a little bit of hot glue and paper clips) to make a super cool set of Christmas lights.
Designing for Humans: Viewing DFM and Industrialization Through the Lens of the Fitts MABA–MABA List
"Operator’s fault" and "Inadequate Training" are the phrases you typically hear when yield loss and stubborn manufacturing issues are discussed. While these factors may play a role, they rarely tell the whole story. This article views DFM and industrialization through the lens of a classic human factors principle; the Fitts MABA-MABA list, and highlights a critical, yet less-discussed factor: the lack of manufacturing-focused human factors considerations in product design. It explores practical examples like Proprioceptive Fatigue and Visual SNR, and shows how lots of chronic manufacturing issues are results of bad upstream design decisions, echoing the fact that in many cases, inspection exists not because it is inherently valuable, but because the design failed to encode correctness directly into the product or process. If you’ve ever wondered why "retraining" never seems to fix a recurring defect, this take on industrialization and manufacturing might explain why.
The Teardown Conference Call for Proposals is Open for Another Week!
The Teardown conference "Call for Proposals" goes until Wednesday, January 15th! Get yours in soon!
Small Language Models (SLMs): The Future of AI is Smaller, Faster, and Closer to the Edge
AI industry is shifting from a "bigger is better" mentality to a focus on efficiency, localization, and real-world utility. The article argues that the AI industry is pivoting from massive, cloud-bound models toward Small Language Models (SLMs) designed for efficiency, speed, and edge deployment. Driven by the need to overcome cloud-centric hurdles like high latency, bandwidth costs, and privacy risks, SLMs (ranging from 100M to 14B parameters) leverage architectural innovations such as quantization, sparse attention, and high-quality synthetic data to deliver specialized intelligence on local hardware. Rather than replacing large models, SLMs represent a shift toward a hybrid intelligence future where the cloud provides depth while the edge provides real-time, sustainable action, ultimately moving the focus of AI progress from raw parameter count to practical, real-world utility.
Requirements, Specifications and Tests
A practical workflow keeps embedded projects predictable and reduces late surprises. Start with a client-driven Set of Requirements, then derive a QA Test Set from those requirements, and write a Technical Spec that maps to the design. The method enforces change control, helps catch feature creep early, and makes final acceptance straightforward for non-engineer testers.
Quickfire Heuristics: A Fast Usability Evaluation Framework for Lean Hardware Teams
That device with the single LED that requires you to count blink patterns just to understand system status. The button you must hold for 8 seconds, which also performs four other actions depending on hold duration. These are not accidents of negligence; they are the predictable output of development processes that have no rigorous usability evaluation component. Usability tends to slip through the gaps of standard engineering reviews, surfacing late, when design flexibility is already gone. This article introduces a framework that adapts Jakob Nielsen's Ten Usability Heuristics, for hardware and embedded systems, translating each principle into concrete evaluation questions for physical interfaces, firmware state machines, constrained displays, and cross-layer interactions. Using a smartwatch as the running example, it also introduces a structured session format, maps the framework to key lifecycle stages, and extends it to manufacturing, test, and field service contexts.
