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Digital PLL's -- Part 2

Neil Robertson — Wed, 15 Jun 2016 11:18:41 +0000

In Part 1, we found the time response of a 2nd order PLL with a proportional + integral (lead-lag) loop filter. Now letâ€™s look at this PLL in the Z-domain [1, 2]. We will find that the response is characterized by a loop natural frequency Ï‰n and damping coefficient Î¶.

Having a Z-domain model of the DPLL will allow us to do three...

Digital PLL's -- Part 1

Neil Robertson — Tue, 07 Jun 2016 14:34:38 +0000

1. Introduction

Figure 1.1 is a block diagram of a digital PLL (DPLL). The purpose of the DPLL is to lock the phase of a numerically controlled oscillator (NCO) to a reference signal. The loop includes a phase detector to compute phase error and a loop filter to set loop dynamic performance. The output of the loop filter controls the frequency and phase of the NCO,...