Verilog Hdl: A Guide to Digital Design and Synthesis
Verilog HDL is a language for digital design, just as C is a language for programming. This complete Verilog HDL reference progresses from the basic Verilog concepts to the most advanced concepts in digital design. Palnitkar covers the gamut of Verilog HDL fundamentals, such as gate, RTL, and behavioral modeling, all the way to advanced concepts, such as timing simulation, switch level modeling, PLI, and logic synthesis. Verilog HDL is a hardware description language (with a user community of more than 50,000 active designers) used to design and document electronic systems. This completely updated reference progresses from basic to advanced concepts in digital design, including timing simulation, switch level modeling, PLI, and logic synthesis.
Why Read This Book
You will get a clear, hands-on introduction to Verilog syntax and modeling styles from gate level through RTL and behavioral descriptions, plus practical coverage of timing simulation, logic synthesis and PLI for real projects. The book is strong on examples and real-use advice, so you can quickly write, simulate, and synthesize modules for FPGAs or custom logic; note that it predates SystemVerilog, so modern verification features are not covered.
Who Will Benefit
Best suited for hardware or embedded engineers (junior to intermediate) who need to design or integrate FPGA/ASIC logic or write synthesizeable RTL that interfaces with firmware or SoC components.
