Mips Risc Architecture
A complete reference manual to the MIPS RISC architecture, this book describes the user Instruction Set Architecture (ISA), by the R2000, R3000, R4000, and R6000 (collectively known as the R-Series) processors, together with an extension to this ISA. Focusing on the new R4000 and R6000 chips, this book is organized into two major sections: Chapters 1 through 6 describe the characteristics of the CPU, while Chapter 7 through 9 describe the Floating Point Unit (FPU). This book describes the general characteristics and capabilities of each RISC processor, along with a description of the programming model, memory management unit (MMU), and the registers associated with each processor. Also included is an overview of the underlying concepts that distinguish RISC architecture from Complex Instruction Set Computer (CISC) architecture.
Why Read This Book
You should read this book if you need a rigorous, low-level reference for the classic MIPS R-series processors — it documents the ISA, registers, MMU, exceptions and FPU behavior you’ll need when writing boot code, low-level firmware, or porting an OS. It also explains RISC design decisions that help you reason about pipeline behavior, exception handling, and performance trade-offs on MIPS systems.
Who Will Benefit
Firmware engineers, OS porters, compiler backend writers, and advanced students who are working on or maintaining MIPS-based embedded systems, bootloaders, or kernel code.
Level: Advanced — Prerequisites: Familiarity with computer architecture basics, assembly language concepts, C programming, and operating-system level concepts (virtual memory, exceptions).
Key Takeaways
- Describe the MIPS programming model including register conventions and calling sequences.
- Decode and use the integer and control-flow instruction set used by R2000–R6000 CPUs.
- Configure and reason about the MIPS MMU, virtual memory layout, and exception handling for OS/firmware code.
- Implement and debug floating-point code using the MIPS FPU (formats, instructions, and exceptions).
- Design low-level firmware, boot code, and trap/interrupt handlers tailored to MIPS R-series behavior.
Topics Covered
- Introduction to MIPS and RISC principles
- Overview of the R-Series processors (R2000, R3000, R4000, R6000)
- MIPS Programmer’s Model and Registers
- Integer Instruction Set and Encoding
- Control Flow, Branching and Calling Conventions
- Memory System, Caches and Load/Store Model
- Memory Management Unit (MMU) and Virtual Memory
- Exceptions, Interrupts and Trap Handling
- Floating Point Unit (FPU) Architecture and Instructions
- Coprocessors and Privileged Architecture
- System-Level Interfaces and Implementation Notes
- Appendices: Instruction encodings, opcode tables, and reference material
Languages, Platforms & Tools
How It Compares
Covers similar low-level, MIPS-specific detail to the MIPS Architecture manuals (from MIPS Technologies) and complements Patterson & Hennessy’s 'Computer Organization and Design', which uses MIPS for examples but is broader and more textbook-oriented.
