VHDL: A Starter's Guide (2nd Edition)
This handy reference gives readers a thorough grounding in the basic concepts and language of VHDL, and encourages them to apply what they have learned using realistic examples. Concepts are followed by examples and tutorials. Adds appendices to support material: Includes a tutorial for a popular VHDL simulator; a handy reference to common VHDL packages; and a detailed template for a VHDL model illustrating the relative ordering of program constructs. Emphasizes development of readers’ intuition and structured thinking about VHDL models without spending excessive time on advanced language features. Provides simulation and laboratory exercises that enable readers to quickly come up to speed in building useful, non-trivial models of digital systems. Provides tutorial descriptions and presentation of programming mechanics unique to CAD tools and environments. Includes examples, extensive use of timing diagrams, event lists and many tutorials for independent student study. Provides sample problems, many of which include worked solutions. Includes viewgraph masters and the VHDL source for all text examples. A useful reference for computer professionals who need to brush up on their VHDL knowledge.
Why Read This Book
You should read this if you need a concise, example-driven introduction to VHDL that gets you from language basics to useful RTL models and testbenches quickly. The book emphasizes intuition and practical examples, so you can apply VHDL to real FPGA/ASIC tasks without getting bogged down in rarely used language corners.
Who Will Benefit
Hardware or firmware engineers with basic digital-logic knowledge who need to write, simulate, and synthesize VHDL for FPGA or ASIC projects.
Level: Beginner — Prerequisites: Basic digital logic (combinational/sequential circuits) and familiarity with general programming concepts; no prior VHDL required.
Key Takeaways
- Write correct VHDL for combinational and sequential logic using behavioral and structural styles.
- Construct and run effective testbenches and simulations to validate HDL designs.
- Organize reusable code with packages, subprograms, and proper entity/architecture separation.
- Translate high-level functional descriptions into synthesizable RTL suitable for FPGAs.
- Apply common synthesis constraints and be aware of language constructs that affect implementability.
- Use a VHDL simulator and follow practical lab exercises to debug and iterate on designs.
Topics Covered
- Introduction to VHDL and digital design workflow
- Basic VHDL language elements: identifiers, lexical rules, and data types
- Concurrent statements and structural modeling
- Sequential statements and processes
- Subprograms, packages, and component declaration
- Designing finite state machines and sequential systems
- Testbenches, stimulus generation, and simulation techniques
- Synthesis considerations and common implementation pitfalls
- Examples and lab exercises: counters, ALU, memory interfaces
- Appendix: using a VHDL simulator (tutorial)
- Appendix: common VHDL packages and templates
- Model templates and coding style guidelines
Languages, Platforms & Tools
How It Compares
More hands-on and beginner-friendly than Bhasker's A VHDL Primer, and less exhaustive than Douglas Perry's Programming in VHDL; ideal if you want practical examples rather than a language reference.
