The Designer's Guide to VHDL, Third Edition (Systems on Silicon)
VHDL, the IEEE standard hardware description language for describing digital electronic systems, has recently been revised. This book has become a standard in the industry for learning the features of VHDL and using it to verify hardware designs. This third edition is the first comprehensive book on the market to address the new features of VHDL-2008.
* First comprehensive book on VHDL to incorporate all new features of VHDL-2008, the latest release of the VHDL standard...helps readers get up to speed quickly with new features of the new standard.
* Presents a structured guide to the modeling facilities offered by VHDL...shows how VHDL functions to help design digital systems.
* Includes extensive case studies and source code used to develop testbenches and case study examples..helps readers gain maximum facility with VHDL for design of digital systems.
Why Read This Book
You should read this book if you want a single, authoritative reference that takes you from VHDL basics through the new language features introduced in VHDL-2008 and shows how to apply them to real hardware design and verification problems. You will learn practical modeling styles, synthesis-aware coding techniques, and robust testbench and verification practices illustrated with extensive examples and case studies.
Who Will Benefit
Digital designers, FPGA/ASIC engineers, and firmware developers with some digital-design background who need to write, verify, or maintain VHDL-based hardware descriptions and want a current, standards-focused reference.
Level: Intermediate — Prerequisites: Basic digital logic (combinational and sequential circuits), familiarity with binary number systems and state machines, and some experience with programming or scripting languages; prior exposure to HDL concepts is helpful but not required.
Key Takeaways
- Describe digital systems at multiple abstraction levels using VHDL (behavioral, RTL, and structural).
- Apply VHDL-2008 language features and idioms to write clearer, more maintainable hardware descriptions.
- Create synthesis-friendly VHDL code and understand synthesis constraints and implementation issues for FPGA/ASIC flows.
- Build robust testbenches and verification artifacts, including assertions and stimulus-driven checks.
- Use packages, generics, and configurations to structure reusable designs and manage largescale projects.
Topics Covered
- 1. Introduction to VHDL and the Design Flow
- 2. Lexical Conventions, Data Types, and Signals
- 3. Sequential and Concurrent Statements
- 4. Subprograms, Packages, and Design Units
- 5. Modeling Techniques: Behavioral, RTL, and Structural
- 6. Time, Processes, and Simulation Semantics
- 7. Generics, Configurations, and Component Instantiation
- 8. Synthesis Considerations and Coding Guidelines
- 9. Testbench Development, Assertions, and Verification
- 10. New and Extended Features in VHDL-2008
- 11. Case Studies and Complete Example Designs
- 12. Interfacing, Libraries, and Tool Flows
- Appendices: Language Reference, Source Listings, and Migration Notes
Languages, Platforms & Tools
How It Compares
More comprehensive and standards-focused than Bhasker's A VHDL Primer and more language- and verification-oriented than Pedroni's Circuits with VHDL, making Ashenden the go-to reference for VHDL-2008 features and best practices.
