An analog-to-digital converter (A/D or ADC) is a peripheral that samples a continuous analog voltage and converts it to a discrete digital value. The result is a binary number proportional to the input voltage, quantized to the converter's resolution (commonly 10 or 12 bits on general-purpose MCUs, though 8-bit and 16-bit or higher variants exist).
In practice
Most MCUs integrate at least one SAR (successive-approximation register) ADC, which is the most common architecture in embedded peripherals. SAR ADCs on general-purpose MCUs typically offer 8 to 12 bits of resolution and sample rates from a few ksps up to several Msps. Higher-end MCUs and dedicated ICs may use sigma-delta ADCs for high-resolution, lower-bandwidth applications (audio, precision sensing), or pipeline/flash ADCs for high-speed data acquisition. The reference voltage (VREF) sets the full-scale input range and directly affects accuracy; using a noisy or poorly regulated VREF is a common source of measurement error.
A/D conversions can be triggered by software, timers, or external events, and results are typically transferred to memory via DMA on MCUs that support it. The ADC peripheral often shares silicon with a multiplexer, allowing multiple analog input channels to be sampled in sequence. Sampling rate and multiplexer switching time interact: switching between channels with differing source impedances without allowing adequate acquisition time is a frequent source of crosstalk and inaccurate readings, as covered in the blog post "Analog-to-Digital Confusion: Pitfalls of Driving an ADC."
Source impedance at the ADC input matters more than many designers expect. Most SAR ADC inputs have a small internal sampling capacitor; if the driving source impedance is too high, the capacitor does not fully charge within the acquisition window, introducing gain error. The recommended practice is to buffer high-impedance sources with an op-amp or to extend the sampling time if the peripheral allows it. Board-level noise (power supply ripple, digital switching noise coupled through the PCB) also degrades SNR, a topic explored in "Here Comes The Noise!"
For isolated or high-common-mode applications, isolated sigma-delta modulators (discussed in "Isolated Sigma-Delta Modulators, Rah Rah Rah!") shift the conversion architecture: the modulator sits on the high-voltage side and transmits a 1-bit data stream across an isolation barrier, with the digital filter and decimation happening on the low-voltage side. This architecture is common in motor drives and power metering where galvanic isolation is required.
Discussed on EmbeddedRelated
Frequently asked
What does ADC resolution mean in practice?
Resolution is the number of bits in the digital output. A 12-bit
ADC divides the input range into 2^12 = 4096 steps. With a 3.3 V reference, each step (1 LSB) represents about 0.8 mV. Higher resolution shrinks the LSB size but does not automatically improve accuracy; noise, reference quality, and layout all limit the effective number of bits (ENOB) actually achieved.
What is the difference between a SAR ADC and a sigma-delta ADC?
A SAR
ADC performs one conversion per sample using a binary-search algorithm and is well suited to moderate resolution (8 to 16 bits) at moderate to high sample rates. A sigma-delta ADC oversamples at a very high rate using a 1-bit (or few-bit) quantizer, then digitally filters and decimates the result to achieve high resolution (16 to 24 bits) at lower bandwidths. SAR ADCs are common in general-purpose
MCU peripherals; sigma-delta ADCs are preferred for audio, weigh scales, and precision instrumentation.
Why does source impedance matter when driving an ADC input?
SAR
ADC inputs typically connect the input to a small sampling
capacitor (often a few picofarads to tens of picofarads) during acquisition. The RC time constant formed by the source impedance and this capacitor limits how quickly the capacitor charges to the input voltage. If the acquisition time is shorter than roughly five RC time constants, the sampled voltage is low by a predictable but often overlooked error. Buffering with a low-output-impedance
op-amp or increasing the acquisition window are the standard remedies.
How can I reduce noise in ADC measurements?
Common approaches include: using a clean, low-noise
VREF (a dedicated reference IC rather than the
MCU supply rail); averaging or oversampling multiple conversions in firmware; triggering conversions when noisy peripherals (switching regulators,
PWM outputs) are quiescent if timing permits; using proper analog layout practices (ground plane, short analog traces, separation from digital switching nodes); and adding a low-pass RC filter at the
ADC input to band-limit noise above the frequency of interest.
What is oversampling and does it really improve resolution?
Oversampling means sampling at a rate higher than the Nyquist rate for the signal of interest and then averaging (decimating) the results. For every factor-of-4 increase in sample count averaged, resolution improves by 1 bit, provided the input signal has sufficient broadband noise to dither the
ADC. In practice, many
MCU firmware examples use 4x or 16x oversampling to squeeze 1 to 2 extra effective bits from a 10- or 12-bit SAR ADC. The MSP430 LaunchPad tutorial series demonstrates this technique in a straightforward embedded context.
Differentiators vs similar concepts
A/D (
ADC) is sometimes confused with the delta-sigma modulator, which is only the front-end stage of a sigma-delta conversion chain, not a complete converter. The full sigma-delta ADC includes the modulator plus a digital decimation filter. ADC is also distinct from
DAC (digital-to-analog converter), which performs the inverse operation. In mixed-signal contexts, "A/D" and "ADC" are interchangeable; datasheets may use either abbreviation.
