The address bus is a set of signal lines, or in modern systems an address phase within a bus protocol or internal fabric, used by a processor or bus master to specify the memory location or peripheral register it wants to read from or write to. In classical parallel bus designs it is typically unidirectional, though some architectures use multiplexed or shared address-data pins that blur this distinction.
In practice
On microcontrollers with an external memory interface — such as the STM32 FSMC/FMC, Kinetis FlexBus, or NXP LPC EMC peripherals — the address bus is brought out to physical pins so that external SRAM, NOR Flash, or NAND Flash can be connected. The width of the bus determines the directly addressable range assuming byte-addressable locations: a 16-bit address bus can address 2^16 = 65,536 locations, a 24-bit bus reaches 16 MB, and so on (word-addressed or otherwise granular systems will differ in byte capacity). Most MCUs that do not need external memory keep the address bus entirely internal.
On deeply embedded 8-bit and 16-bit parts — PIC, AVR, MSP430 — the address bus is almost always internal, and developers rarely interact with it directly. On 32-bit Cortex-M devices, the architectural address space is 4 GB (32-bit addressing), divided into regions for Flash, SRAM, peripherals, and vendor-specific use according to ARM's Cortex-M memory map specification, which vendors build on with their own peripheral regions and aliases. Peripheral registers are accessed through this same address space, which is why a GPIO register and a UART register each have a unique 32-bit address.
A common pitfall when connecting external memory is bus contention or floating lines. If address lines are left unconnected or share a bus with multiple devices lacking proper chip-select logic, data corruption or bus lockup can result. Pull resistors, proper PCB trace length matching, and correct chip-select decoding are all relevant. Hardware bugs introduced at this level can be subtle and intermittent, as discussed in the EmbeddedRelated post "The habitat of hardware bugs."
Address bus width also affects linker scripts and memory-mapped I/O code. If a pointer is cast to access a peripheral at a fixed address, the address must fit within the physical bus width and fall within the region the bus fabric actually decodes. Accessing an unmapped address on Cortex-M cores typically triggers a BusFault, which escalates to HardFault if BusFault is not enabled; behavior on other architectures varies.
Frequently asked
What is the difference between the address bus and the data bus?
The address bus carries the location the processor wants to access; the
data bus carries the value being read or written at that location. They are separate signal groups, though some architectures and external memory interfaces use address/data multiplexing on shared pins to reduce pin count — common on 8051 derivatives and some parallel
Flash interfaces.
Does address bus width directly determine how much memory a processor can use?
It sets the upper bound on directly addressable locations. A 32-bit address bus gives a 4 GB address space, but the usable memory is further constrained by how much of that space the chip vendor actually maps to
RAM,
Flash, or peripherals. On Cortex-M devices, large portions of the 4 GB space are reserved or unpopulated on any given
MCU variant.
Is the address bus relevant on MCUs with no external memory interface?
Yes, but only internally. Even when no address pins are exposed, every memory access and peripheral register read/write travels over an internal address bus fabric — typically an
AHB or
APB interconnect on ARM-based devices. Developers encounter this indirectly through fixed peripheral base addresses in datasheets and header files.
What happens if an address beyond the valid range is accessed?
Behavior depends on the architecture and bus fabric. On ARM Cortex-M cores, accessing an unmapped address typically causes a BusFault (escalated to HardFault if BusFault is not enabled). On simpler 8-bit or 16-bit MCUs with no memory protection, the access may silently return garbage data or alias to another region, making such bugs difficult to catch.
What is address/data multiplexing and where does it appear in embedded systems?
Some processors output address and data on the same physical pins in time-separated phases to reduce pin count. Classic examples include the Intel 8051 (ports P0 and P2 serve as AD0-AD7 and A8-A15) and some parallel
NOR Flash interfaces. An external latch IC — commonly a 74HC373 or 74HC573 — captures the address during the address phase so it remains stable while data is transferred.
Differentiators vs similar concepts
The address bus is often discussed alongside the
data bus and control bus as the three classical components of a processor bus. The data bus carries the actual values read or written; the control bus carries timing and direction signals such as read/write strobes, chip selects, and clock. In modern SoC designs, these three logical groups are subsumed into higher-level bus protocols such as
AHB,
AXI, or
APB, where address and data phases are defined by the protocol rather than by discrete parallel signal groups.
