AHB (Advanced High-performance Bus) is a high-speed, pipelined on-chip bus from ARM's AMBA specification, designed to connect processors, memories, and high-bandwidth peripherals such as DMA controllers, USB, and Ethernet MACs within an SoC. It forms the backbone interconnect in the majority of ARM Cortex-M based microcontrollers, and appears in peripheral or legacy bus segments of many Cortex-A application processors, which more commonly use AXI as their primary interconnect.
In practice
In most ARM Cortex-M MCUs (STM32, LPC, SAM, nRF52, Kinetis, and similar families), the AHB sits at the top of the on-chip bus hierarchy. The CPU, DMA controllers, and memories are typically masters or slaves on the AHB fabric, while slower peripherals such as timers, UART, SPI, and I2C hang off a downstream APB (Advanced Peripheral Bus) bridge. This two-tier arrangement lets high-throughput data movement happen at full core clock speed without being held up by slower peripheral transactions.
AHB-Lite, introduced in AMBA 3, is among the most commonly implemented variants in microcontroller-class devices. It defines a single-master subset of the full AHB protocol, which is simpler to implement in silicon than the multi-master arbitration of the full AHB. Though AHB-Lite is prevalent, some MCU families employ more elaborate bus matrices or mix AHB-Lite with proprietary interconnects. AXI (Advanced eXtensible Interface), which predates AMBA 4 but was significantly extended in later AMBA revisions, has largely replaced AHB for the highest-bandwidth paths in application-class SoCs, but AHB and AHB-Lite remain prevalent on Cortex-M parts.
From a firmware perspective, AHB details are almost always invisible: the bus protocol is handled entirely in hardware, and you interact with peripherals through their memory-mapped registers. The bus topology does matter in a few practical situations. Bus matrix implementations (used in, for example, STM32F4 and STM32H7 series) allow multiple AHB masters to access different slaves simultaneously, which affects DMA throughput and latency. Misunderstanding which bus a peripheral sits on can also lead to unexpected clock-enable requirements: on STM32 devices, peripherals on AHB, APB1, and APB2 each have separate RCC enable bits and may run at different clock frequencies.
When reviewing an MCU datasheet or reference manual, the bus architecture diagram tells you which peripherals are on AHB versus APB. Peripherals on AHB (typically DMA, GPIO on some STM32 lines, Flash interface, Ethernet, USB OTG) run at or near the core clock, while APB peripherals run at a divided rate. This directly impacts maximum achievable sample rates, timer resolution, and DMA burst performance.
Frequently asked
What is the difference between AHB, AHB-Lite, and AHB5?
Full AHB (
AMBA 2) supports multiple bus masters with an arbiter. AHB-Lite (AMBA 3) is a simplified single-master subset and is the variant found in the vast majority of Cortex-M microcontrollers. AHB5 (AMBA 5) adds TrustZone security attribution signals and is used in Cortex-M33 and Cortex-M55 based devices such as the STM32L5 and STM32U5 series.
How fast is AHB?
AHB is synchronous and runs at a frequency determined by the SoC's clock configuration, subject to constraints imposed by the silicon process, implementation timing requirements, and bus matrix design. On Cortex-M microcontrollers, this is typically the core clock or a direct division of it. For example, STM32H7 parts can run the AHB at up to 240 MHz, while STM32F1 parts run it at up to 72 MHz. There is no fixed 'AHB speed'; the achievable limit depends on the specific implementation.
Do I need to care about AHB when writing firmware?
Mostly no. The bus protocol is transparent hardware. However, you do need to be aware of it when enabling peripheral clocks (each bus domain has its own enable register, e.g., RCC_AHBxENR on STM32 parts), when calculating maximum
DMA throughput, and when understanding why two peripherals might run at different clock rates even on the same chip.
Why do some MCUs have multiple AHB buses (AHB1, AHB2, AHB3)?
Splitting peripherals across multiple AHB segments allows simultaneous accesses by different masters without contention, and lets the designer assign different peripherals to different power or security domains. On STM32H7 parts, for instance, peripherals and interfaces are distributed across multiple AHB segments with independent clock and power controls; the exact mapping of AHB domains to CPU subsystems,
flash, and external memory interfaces varies by subfamily and should be confirmed in the relevant reference manual.
How does AHB relate to AXI?
Both are ARM
AMBA bus standards, but they target different performance points.
AXI (Advanced eXtensible Interface) supports separate read and write channels, out-of-order transactions, and higher burst throughput, making it the preferred interconnect for high-end Cortex-A SoCs. AHB and AHB-Lite remain common on Cortex-M parts where AXI's added complexity is unnecessary. On mixed designs such as the STM32MP1 or i.MX RT series, AXI is often used in the high-performance CPU subsystem while AHB bridges connect to lower-bandwidth peripheral clusters.
Differentiators vs similar concepts
AHB is often confused with
APB (Advanced Peripheral Bus) and
AXI (Advanced eXtensible Interface), all of which are part of the ARM
AMBA family. APB is a low-power, low-complexity bus intended for slow peripherals (
UART,
SPI, timers); it is non-pipelined and runs at a divided clock relative to AHB. AXI is a higher-performance successor designed for application-class SoCs, supporting out-of-order transactions and separate read/write channels; it is typically found on Cortex-A parts rather than Cortex-M. AHB sits between the two in performance and complexity and is the dominant interconnect in Cortex-M microcontrollers.
