A cache line is the smallest unit of data transferred between main memory and a cache. Rather than fetching individual bytes or words, the cache typically reads and writes memory in fixed-size aligned blocks -- commonly 32 or 64 bytes on processors that have hardware caches, though 128-byte lines also exist on some cores.
In practice
Cache lines matter most on application-class processors (Cortex-A, RISC-V with L1/L2 caches, x86-class SoCs) rather than on typical Cortex-M or 8/16-bit MCUs, which usually have no data cache or only a small instruction cache. On cache-equipped processors, every cache miss causes the entire containing cache line to be fetched from slower memory, so access patterns and data layout have a large impact on performance.
Struct layout is a common place where cache line behavior shows up. If two frequently accessed fields sit in the same 64-byte line, reading one field brings the other into cache for free. Conversely, padding a struct or scattering related data across multiple structs can cause extra cache misses. Hot data -- variables read frequently in a tight loop -- should be grouped together and, on some platforms, aligned to a cache line boundary using compiler attributes such as `__attribute__((aligned(64)))`.
False sharing is a pitfall specific to multicore systems. If two CPU cores each write to different variables that happen to reside in the same cache line, the hardware coherency protocol forces the line to bounce between cores on every write, killing performance even though the cores are touching distinct memory locations. The fix is to pad or align the variables so they occupy separate cache lines.
On processors with software-managed cache control (common in DSPs and some Cortex-R/A parts), explicit cache maintenance operations -- clean, invalidate, or flush -- operate on cache lines or ranges of them. Getting these wrong when sharing buffers between a CPU and a DMA engine is a frequent source of hard-to-reproduce data corruption bugs.
Frequently asked
What is a typical cache line size?
32 bytes on ARM Cortex-A8 and many older cores; 64 bytes on Cortex-A53/A55/A72 and most modern 32-bit and 64-bit application processors. Some DSPs and high-performance cores use 128 bytes. The size is fixed by the hardware and is documented in the processor's technical reference manual.
Do Cortex-M microcontrollers have cache lines I need to worry about?
Most Cortex-M0/M0+/M3/M4 devices have no data
cache, so cache line concepts do not apply to data accesses on those parts. The Cortex-M7 optionally includes a data cache with 32-byte lines, though the available cache size and exact configuration vary by vendor implementation. If you are using a Cortex-M7 device such as the STM32H7 or i.MX RT series with the D-cache enabled, cache maintenance and false sharing do become relevant.
What is false sharing and why is it a problem?
False sharing occurs when two cores independently write to different variables that happen to occupy the same
cache line. The cache coherency protocol treats the entire line as a unit, so each write by one core invalidates the other core's copy, forcing a re-fetch. The variables are logically independent, but the hardware serializes the accesses anyway. The result is a significant and non-obvious performance penalty on multicore Cortex-A and similar processors.
How do I find the cache line size at runtime or compile time?
On ARM Cortex-A processors running Linux, the value is available via `/sys/devices/system/cpu/cpu0/
cache/index0/coherency_line_size` or through the CTR_EL0 register in AArch64. In bare-metal code, read the Cache Type Register (CTR or CCSIDR) defined in the ARM Architecture Reference Manual. For portability, many codebases define a macro such as `CACHE_LINE_SIZE 64` based on the known target hardware.
When do I need to manually invalidate or flush a cache line?
On processors with hardware-coherent caches shared between all cores (common on Cortex-A clusters using MESI or MOESI protocols), the hardware keeps caches consistent and you typically do not need manual maintenance for CPU-to-CPU sharing. Manual
cache operations are needed when a
DMA engine or other bus master writes to memory that the CPU has cached, or when the CPU writes a buffer the DMA engine will read. In those cases you must clean (write back) or invalidate the relevant cache lines before or after the DMA transfer to avoid stale data.
Differentiators vs similar concepts
A
cache line is often confused with a cache way or a cache set, which are organizational units within a set-associative cache, not transfer units. A cache way is one bank of cache storage within a set; a cache set is the group of ways that a given address maps to. The cache line is the data granule -- the actual bytes moved -- while ways and sets describe how those lines are organized and located within the cache array. Cache line is also distinct from a memory page (typically 4 KB), which is the granule used by the
MMU for virtual-to-physical address translation and permission management.
