A CPLD (Complex Programmable Logic Device) is a category of reconfigurable digital logic IC that uses an array of macrocells connected through a programmable interconnect to implement combinational and registered logic. CPLDs sit between simple PLDs (SPLDs such as PALs and GALs) and FPGAs in terms of capacity and complexity, typically offering hundreds to a few thousand logic gates equivalent with non-volatile, instant-on configuration.
In practice
CPLDs are commonly used in embedded designs to offload glue logic tasks that would otherwise require several discrete 74-series ICs: bus arbitration, address decoding, signal level translation, chip-select generation, and simple state machines. Their non-volatile configuration (typically stored in on-chip flash or EEPROM) means they are ready immediately at power-on without a separate configuration bitstream loader, which makes them easier to integrate into systems where startup sequencing matters.
In practice, CPLDs are programmed using HDLs such as VHDL or Verilog (or schematic capture in vendor tools). The logic is synthesized and fitted into the macrocell array by vendor toolchains such as Xilinx ISE/Vivado (for the XC9500/CoolRunner families), Intel Quartus (for the MAX series, including MAX II and MAX V), or Lattice Diamond/Radiant (for the ispMACH and MachXO families). The EmbeddedRelated posts "VHDL tutorial - A practical example - part 1 - Hardware" and "VHDL tutorial - A practical example - part 2 - VHDL coding" demonstrate this workflow hands-on.
A key practical limitation is capacity: most CPLDs top out at a few hundred to a few thousand macrocells, so designs requiring large memories, DSP blocks, or tens of thousands of logic elements are better served by an FPGA. CPLDs also typically lack dedicated RAM blocks and multiplier primitives. On the other hand, CPLDs consume less static power than most FPGAs (some families are in the low-milliwatt range), and their simpler, uniform interconnect structure gives predictable, fixed propagation delays -- useful when timing must be deterministic without place-and-route variability.
Discussed on EmbeddedRelated
Frequently asked
What is the internal structure of a CPLD, and how does it differ from a PAL or GAL?
A CPLD consists of multiple logic blocks (each containing several macrocells with AND-OR logic planes and a D/T flip-flop) connected by a global programmable interconnect matrix. A PAL or GAL is essentially a single such block, so a CPLD is architecturally a collection of SPLDs tied together with a routable bus. This gives CPLDs much higher capacity and the ability to implement multi-output state machines and more complex combinational logic while retaining the predictable, sum-of-products structure.
How do CPLDs compare to FPGAs, and when should I choose one over the other?
CPLDs use a programmable interconnect with non-volatile configuration storage (
flash or
EEPROM) and are ready at power-on with no external configuration memory needed. Most FPGAs use
SRAM-based configuration cells that must be loaded from external flash at startup, offer far greater logic density, and include dedicated resources like block
RAM,
DSP slices, PLLs, and high-speed transceivers (though some
FPGA families also offer non-volatile configuration). Choose a CPLD for glue logic, address decoding, simple state machines, or any task where instant-on and non-volatility matter and gate count is modest (under a few thousand LUT-equivalents). Choose an FPGA when capacity, embedded memory, or DSP performance are required.
Do CPLDs need external configuration memory at startup?
On almost all modern CPLDs, no. Families such as the Xilinx XC9500XL, Intel MAX II/V, Lattice ispMACH 4000, and MachXO2/3 store the configuration in on-chip non-volatile memory (
flash or
EEPROM). The device is configured and running within microseconds of power-on. This contrasts with
SRAM-based FPGAs (such as the Xilinx 7-series or Intel Cyclone/Arria families), which require an external
SPI or parallel flash and a configuration controller.
What languages and tools are used to program a CPLD?
CPLDs are typically programmed using VHDL or Verilog, synthesized and fitted with vendor tools: Xilinx ISE or Vivado for XC9500/CoolRunner families, Intel (Altera) Quartus Prime for MAX series devices, and Lattice Diamond or Radiant for ispMACH and MachXO families. Many vendors also support schematic capture for simple designs. The resulting programming file (commonly in JEDEC or SVF format) is transferred to the device via
JTAG, which is widely supported across CPLD families, though exact interface support varies by vendor and device.
Can I use a CPLD to interface an old parallel bus peripheral to a modern MCU?
Yes, this is one of the most common CPLD use cases. A CPLD can translate bus widths, generate chip-select and read/write strobes from
SPI or
GPIO signals, retime asynchronous signals, or multiplex address and data buses. Because CPLDs have deterministic propagation delays (often specified as a single tPD figure per family and speed grade), they are well suited to glue logic where setup and hold times to external memory or peripherals must be carefully controlled.
Differentiators vs similar concepts
CPLDs are frequently confused with FPGAs. The core distinctions: CPLDs use a sum-of-products macrocell architecture with a global interconnect matrix, while FPGAs use a fine-grained sea of LUTs with a hierarchical routing fabric. CPLDs store configuration in non-volatile on-chip memory (instant-on, no external
flash needed on most families); most FPGAs use
SRAM configuration cells that require loading at every power-up, though some
FPGA families also offer non-volatile configuration options. CPLDs are capacity-limited (typically topping out at a few thousand macrocells), whereas FPGAs scale from tens of thousands to millions of LUT equivalents. CPLDs are also sometimes confused with SPLDs (PALs, GALs): a CPLD is architecturally a set of interconnected SPLD-like blocks, with correspondingly greater capacity and the ability to route signals between blocks.
