A data bus is a set of parallel signal lines that transfer data between two or more components in a system, such as a CPU, memory, and peripherals. It defines the physical width (number of bits transferred simultaneously); the electrical and timing rules governing transfers belong to the broader bus interface specification, though the two are closely related.
In practice
In microcontroller and microprocessor designs, the data bus width directly influences throughput and code density. 8-bit MCUs such as the PIC16 or ATmega series have an 8-bit data bus, meaning a 16-bit memory access typically requires two bus cycles to transfer. 16-bit and 32-bit parts (MSP430, ARM Cortex-M) can transfer wider operands in a single cycle, which matters for performance-critical loops and for peripheral register access. On many higher-end SoCs, internal interconnect buses are often 64 or 128 bits wide as a general trend, even when the programmer-visible registers are 32-bit, though actual widths vary across different internal fabrics and designs.
External memory buses appear frequently when an MCU or MPU needs to address off-chip SRAM, NOR flash, or an LCD controller. Parts such as the STM32F4 and STM32H7 families include a Flexible Memory Controller (FMC) that exposes an 8- or 16-bit parallel data bus to external devices. For controllers with configurable bus timing, the setup, hold, and cycle width parameters should be configured in firmware to match the attached device's datasheet, as mismatches can be a source of subtle data corruption, though some timing is fixed in hardware or set by board design.
A key practical consideration is bus contention: if two drivers assert conflicting logic levels on shared data lines at the same time, the result is indeterminate and can damage output drivers. On a bidirectional bus, the driving side must release (tri-state) the lines before the other device drives them. Properly inserting bus turnaround cycles and ensuring correct output-enable sequencing are critical steps when designing or debugging parallel bus interfaces.
Bus width also interacts with byte ordering in transfers. When a 32-bit value is written across a 16-bit data bus, the order in which the high and low halfwords are transferred depends on both the hardware design and the software accessing it. Byte-lane enables (such as the UB#/LB# signals on 16-bit SRAM) control which portion of the bus is written, and getting this wrong produces silent data corruption that is hard to trace. The EmbeddedRelated post "Endianness and Serial Communication" discusses related byte-ordering pitfalls in transferred data.
Frequently asked
What is the difference between the data bus, address bus, and control bus?
These three buses together form the classic parallel bus interface. The
address bus carries the location being accessed (read or write target). The data bus carries the actual value being transferred. The control bus carries signals such as read/write select, chip enable, byte enables, and ready/wait. On many modern MCUs the address and control signals are multiplexed or abstracted away inside the chip, but the distinction is still useful when working with external memory or peripheral buses.
Does bus width equal the MCU's word size?
Not necessarily. The programmer-visible word size (the width of the general-purpose
registers) and the internal or external data bus width can differ. For example, a 32-bit Cortex-M
MCU may access an external peripheral over an 8-bit FMC bus. Internally, some 8-bit AVR devices use an 8-bit data bus even though they have a 16-bit program counter accessed as two bytes.
What causes bus contention and how do I avoid it?
Bus contention occurs when two output drivers simultaneously drive the same data line to opposite logic levels. On a bidirectional bus, the currently driving side must tri-state its outputs before the other device begins driving. Always ensure there is a defined turnaround time between direction changes, and verify it in both your schematics and your bus timing configuration
registers.
Logic analyzer captures are invaluable for spotting contention during bring-up.
How do byte lane enables work on a 16-bit or 32-bit data bus?
Byte lane enables (often labeled UB#/LB# on 16-bit
SRAM, or BE0#-BE3# on 32-bit devices) allow the master to write only specific byte lanes while leaving others unchanged. This is necessary when firmware writes a single byte to a device wired on a wider bus. If the byte enables are wired or configured incorrectly, byte-swapped or partially overwritten data results, often silently.
Are parallel data buses still common in new embedded designs?
Parallel external memory buses have become less common at the board level as serial interfaces like
QSPI, OSPI, and
DDR SDRAM with dedicated controllers have taken over for high-density storage and fast memory. However, parallel data buses remain prevalent inside SoCs (connecting CPU cores to caches and internal peripherals via
AHB/
AXI-class interconnects) and are still used externally in designs requiring parallel
NOR flash,
SRAM, or parallel LCD interfaces.
Differentiators vs similar concepts
A data bus is often contrasted with a serial bus. A parallel data bus transfers multiple bits simultaneously over dedicated lines, offering higher single-transfer bandwidth at the cost of pin count and signal integrity complexity at speed. A serial bus (
SPI,
I2C,
CAN,
USB) transfers bits sequentially over one or a few lines, trading raw parallel bandwidth for simpler wiring and easier PCB routing; in many contexts serial buses also offer better noise immunity over longer distances, though this is a useful rule of thumb rather than a universal property. At sufficiently high frequencies, serial interfaces can match or exceed practical parallel bus throughput because serial signals are easier to terminate and synchronize.
