Ethernet is a family of wired networking standards (IEEE 802.3) that define the physical layer signaling, frame format, and media access rules for local area networks -- though specific details vary across the many amendments and variant specifications within the 802.3 family. It operates at speeds ranging from 10 Mbps (10BASE-T) through 100 Mbps (Fast Ethernet), 1 Gbps (Gigabit Ethernet), and beyond, and remains the dominant wired LAN technology in both IT infrastructure and embedded systems.
In practice
In embedded systems, Ethernet most commonly appears at 10/100 Mbps. Many microcontrollers and SoCs integrate a MAC (Media Access Controller) peripheral on-chip, while the PHY (Physical Layer transceiver) is a separate external chip connected via an MII, RMII, or RGMII bus. The MAC handles frame assembly, CRC generation, and (in half-duplex configurations) collision detection logic; the PHY handles analog signaling, line coding, and typically auto-negotiation over the physical cable. On smaller or cost-sensitive designs that lack an integrated MAC, standalone Ethernet controllers can offload MAC and PHY functions -- and sometimes TCP/IP stack processing -- to an external chip communicating with the host MCU over SPI. For example, the WIZnet W5500 integrates a MAC and a hardware TCP/IP offload engine, while the Microchip ENC28J60 integrates a MAC and PHY but requires the host to run the network stack.
The software stack above the hardware typically follows a layered model: at minimum, an application needs an IP layer (IPv4 or IPv6), UDP or TCP, and usually ARP and ICMP. On bare-metal or RTOS-based targets, lightweight stacks such as lwIP are common. lwIP can run in a "raw API" (callback-driven, no per-socket threads) or a BSD-socket-compatible mode. The choice has direct consequences for RAM usage -- lwIP in a minimal raw-API configuration can fit in tens of kilobytes, whereas a full socket-layer build tends to require more heap for pbuf pools and socket state, though exact figures vary significantly with configuration and application behavior.
Frame handling is a key embedded pitfall. Ethernet frames arrive asynchronously and must be copied from the MAC's RX FIFO or DMA descriptor ring quickly enough to avoid overruns. On low-end MCUs, interrupt-driven or DMA-driven receive paths are essential. Zero-copy descriptor-ring designs (as used by the STM32 Ethernet MAC with its DMA engine) can avoid the cost of memcpy, though realizing true zero-copy in practice still requires careful buffer sizing, cache coherency handling, and buffer ownership discipline between the application and the DMA hardware.
Deterministic latency is a concern in industrial and real-time applications. Standard Ethernet does not guarantee bounded delivery times, which is why protocols such as EtherCAT, PROFINET IRT, and the IEEE 802.1 TSN (Time-Sensitive Networking) suite of standards extend or constrain the 802.3 standard for hard real-time use -- with TSN standards such as 802.1AS (time synchronization) and 802.1Qbv (traffic shaping) providing bounded latency properties under defined network conditions. If a project requires cycle-accurate industrial networking, it is worth evaluating whether a standard lwIP-over-Ethernet stack is sufficient or whether a dedicated EtherCAT or TSN controller is needed.
Frequently asked
What is the difference between the MAC and the PHY, and which one is usually on the MCU?
The MAC (Media Access Controller) handles the data-link layer: frame delimiting, address filtering,
CRC computation, and flow control. The PHY handles physical-layer signaling: encoding bits onto the wire, auto-negotiation, and link-state detection. Many mid- to high-end MCUs and SoCs (for example, STM32F4/F7/H7, i.MX RT, Microchip SAMA5) integrate a MAC but not a PHY. The PHY is a separate IC -- common choices include the LAN8720A, KSZ8081, or DP83848 -- connected to the MAC via RMII (typically a 50 MHz, 2-bit-wide interface) or
MII (25 MHz, 4-bit-wide).
Can Ethernet be used on small MCUs without a built-in MAC?
Yes. Devices like the WIZnet W5500 integrate both the MAC and a hardware
TCP/IP offload engine and connect to the host via
SPI at up to 80 MHz. The Microchip ENC28J60 integrates a MAC and PHY but leaves the IP
stack to host software. These options trade raw throughput and flexibility for reduced host-side complexity and are practical on MCUs with limited peripherals, such as many 8/16-bit or lower-end Cortex-M0 parts.
What lightweight TCP/IP stacks are commonly used in embedded Ethernet designs?
lwIP (Lightweight IP) is the most widely used. It is BSD-licensed, supports IPv4 and IPv6, TCP,
UDP, DHCP, DNS, ICMP, and HTTP, and can be configured down to roughly 40 KB of ROM and 15-20 KB of
RAM for a minimal build, though real deployments typically require more. uIP is a smaller alternative but has largely been superseded by lwIP. Some RTOS vendors (
FreeRTOS+TCP, Zephyr's networking
stack) provide their own implementations. For hardware-offload chips like the W5500, vendor-supplied socket-API libraries are used instead.
Why does Ethernet sometimes drop packets on a resource-constrained MCU?
The most common cause is RX buffer overrun: frames arrive faster than the software can drain the MAC's receive
FIFO or descriptor ring. This is especially likely if the receive path runs in a polling loop or if
interrupts are masked for long periods. Solutions include
DMA-driven receive with a properly sized descriptor ring, zero-copy buffer management to avoid memcpy overhead, and ensuring the network task or ISR has adequate real-time priority. Also confirm that the MAC's RX FIFO thresholds and DMA burst sizes are configured correctly for your specific
MCU -- defaults are often not optimal.
Is standard Ethernet suitable for real-time industrial applications?
Standard IEEE 802.3 Ethernet does not provide bounded
latency guarantees, so it is generally not suitable for hard real-time control loops on its own. Industrial variants address this in different ways: EtherCAT uses on-the-fly frame processing in dedicated slave controllers; PROFINET IRT reserves cyclic time slots at the switch level; IEEE 802.1 TSN (Time-Sensitive Networking) is a suite of standards that adds traffic shaping and time-aware scheduling to the 802.3 framework, providing bounded latency under defined conditions. Choosing the right approach depends on your cycle time requirements, network topology, and available hardware support.
Differentiators vs similar concepts
Ethernet (IEEE 802.3) is often conflated with
TCP/IP or "networking" in general. Ethernet defines only the physical and data-link layers -- frame format, addressing (MAC addresses), and media access. TCP/IP is a separate, higher-layer protocol suite that runs over Ethernet but also runs over Wi-Fi, cellular, and other link layers. Separately, Ethernet is sometimes confused with EtherCAT or PROFINET: both use Ethernet frames and cabling, but they add their own real-time scheduling and application-layer protocols on top, and require dedicated slave controller hardware (e.g., the ET1100 ASIC for EtherCAT) that standard Ethernet controllers cannot substitute for.
