I2S (Inter-IC Sound) is a synchronous serial bus protocol developed by Philips (now NXP) specifically for transferring digital audio data between ICs, such as between a microcontroller or DSP and a codec, DAC, or ADC. It uses separate lines for clock, word-select (channel), and serial data, keeping audio data isolated from control/configuration traffic.
In practice
I2S appears most often as the audio data path in embedded designs that include a digital audio codec, external DAC, or digital microphone. A typical setup has a microcontroller or SoC acting as the bus master, generating the bit clock (BCLK) and word-select (WS, also called LRCLK) signals, while one or more peripheral devices act as slaves that source or sink the serial audio stream. Some codecs can themselves generate the clocks, making the MCU the slave. The roles are configurable on many MCU I2S peripherals, though some hardware blocks have fixed or limited role support.
The word-select line toggles at the audio sample rate (commonly 8 kHz, 44.1 kHz, or 48 kHz) and indicates whether the current data belongs to the left or right channel. The bit clock runs at a multiple of the sample rate determined by the word length and channel count -- for stereo 32-bit audio at 48 kHz, BCLK must be at least 48000 x 2 x 32 = 3.072 MHz. Getting these clock relationships right, especially when the sample rate must be derived from a system PLL that is also serving other peripherals, is one of the most common sources of subtle audio problems such as pitch shift or sample-rate mismatch.
Several variants and extensions exist alongside the original Philips standard. Left-Justified and Right-Justified (sometimes called Sony, though naming is inconsistent across vendors) modes shift the timing of data relative to WS edges. TDM (Time-Division Multiplexed) mode extends the concept to more than two channels on a single data line, used in multi-channel audio systems. PDM (Pulse-Density Modulation), used by many MEMS microphones such as the Knowles SPH0645 or the ST MP34DT01, is a related but distinct one-bit audio signaling format -- not a bus protocol in the same sense as I2S -- often conflated with I2S; PDM uses a single-bit oversampled stream rather than multi-bit words and requires decimation filtering in the receiver.
On the software side, I2S transfers are almost always handled by DMA rather than CPU polling, because audio data arrives at a fixed rate and any CPU stall that causes a missed transfer produces an audible glitch. Double-buffering the DMA descriptors (ping-pong buffering) is the standard technique to allow one buffer to be processed by the application while the other is filled or drained by DMA.
Frequently asked
What is the difference between I2S and I2C?
Despite the similar names, I2S and
I2C are unrelated protocols. I2C (Inter-Integrated Circuit) is a two-wire, addressable, bidirectional bus used for low-speed control and configuration traffic -- setting
registers on a
codec, for example. I2S is a separate, dedicated audio-data bus that carries the actual PCM audio samples. In a typical audio design both are present: I2C configures the codec's sample rate, volume, and routing, while I2S carries the audio stream.
How do I pick the correct BCLK frequency?
BCLK must be at least sample_rate x channels x bits_per_sample. For stereo 16-bit audio at 48 kHz that is 48000 x 2 x 16 = 1.536 MHz; for stereo 32-bit at 48 kHz it is 3.072 MHz. Some peripherals allow BCLK to be higher than the minimum (extra cycles are ignored), but the WS frequency must exactly match the sample rate. Errors here typically cause pitch shift or corrupted audio rather than an obvious hard fault, making them tricky to diagnose without an oscilloscope or
logic analyzer.
What is the difference between standard I2S, Left-Justified, and Right-Justified modes?
In standard (Philips) I2S, the MSB of each sample appears one BCLK cycle after the WS edge. In Left-Justified mode, the MSB appears on the same BCLK cycle as the WS edge -- there is no one-cycle delay. In Right-Justified (Sony) mode, the LSB of the sample is aligned to the next WS edge. Most
MCU I2S peripherals support all three modes via a configuration register, and the choice must match what the attached
codec expects.
Can I use I2S to interface a PDM MEMS microphone?
Not directly without hardware or firmware support for PDM decoding. PDM microphones such as the Knowles SPH0645 or ST MP34DT01 output a 1-bit oversampled bitstream that requires a decimation (CIC or sinc) filter to produce PCM samples. Some MCUs include a dedicated PDM interface with hardware decimation -- STM32 parts with a DFSDM peripheral and certain nRF52/nRF53 series SoCs are examples. Others allow the I2S peripheral to clock the PDM data in, leaving the decimation to software or a
DSP.
Why is DMA essentially mandatory for I2S, and how is it typically structured?
Audio samples arrive at a fixed, relentless rate set by the sample clock. If the CPU is busy handling another
interrupt or memory operation when a sample is due, the data is lost or repeated, producing an audible click or dropout.
DMA removes the CPU from the sample data path, though the CPU still services buffer interrupts and manages the audio pipeline. The standard pattern is ping-pong (double) buffering: two equal-sized buffers are allocated, and the DMA alternates between filling (or draining) them. A half-transfer interrupt fires when the first half is ready, and a transfer-complete interrupt fires when the second half is ready, giving the application a full buffer period to process audio before the DMA wraps around.
Differentiators vs similar concepts
I2S is frequently confused with
I2C because of the similar name, but the two are unrelated -- I2C is a general-purpose addressable control bus, while I2S is an audio-data streaming bus. I2S is also confused with PDM, a one-bit oversampled audio signaling format used by many MEMS microphones; PDM requires decimation filtering to produce the multi-bit PCM words that I2S carries natively. TDM (Time-Division Multiplexing) extends I2S to more than two channels and is sometimes treated as a separate interface, though many
MCU peripherals support both from the same hardware block.
