JTAG (Joint Test Action Group) is a standardized interface (IEEE 1149.1) originally designed for boundary-scan testing of PCBs, and widely adopted as an on-chip debug and programming interface for processors, FPGAs, CPLDs, and complex MCUs. It uses a four-wire serial protocol (TDI, TDO, TCK, TMS, plus an optional TRST reset line) to access an on-chip test access port (TAP) and a chain of internal registers.
In practice
JTAG is widely used for programming and debugging ARM Cortex-A/R/M cores, RISC-V processors, FPGAs (Xilinx/AMD, Intel/Altera, Lattice), DSPs, and many complex SoCs. For ARM Cortex-M targets specifically, JTAG and the two-wire SWD (Serial Wire Debug) protocol share the same DAP (Debug Access Port) hardware; most Cortex-M debug probes (J-Link, CMSIS-DAP, ST-LINK, OpenOCD-compatible adapters) support both. Many 8-bit and low-pin-count MCUs instead use vendor-specific two- or three-wire interfaces such as ICSP, debugWIRE, or SWIM -- though which interfaces are available varies significantly by specific part and family, with some variants within a family supporting JTAG while others do not -- so JTAG is not universal across all embedded targets.
In day-to-day embedded work, a JTAG debug probe lets you set hardware breakpoints, inspect and modify registers and memory, step through code, and flash firmware while the target is running or halted. This is substantially more capable than printf-style instrumentation alone -- though instrumentation techniques (as covered in "Debug, visualize and test embedded C/C++ through instrumentation" and "Tracing code and checking timings") complement JTAG-based debugging rather than replace it. JTAG also underpins higher-bandwidth trace features: on Cortex-A/R cores and some Cortex-M parts, JTAG can carry CoreSight ETM trace data in certain configurations, though ETM trace is often output over separate dedicated trace pins rather than the JTAG interface itself.
On PCBs with multiple ICs that support JTAG, the TAPs can be daisy-chained so a single connector reaches every device. This is common on boards combining an FPGA with a processor or multiple FPGAs. The chain must be correctly described to the tool (device count, IR lengths) or access will fail. A missing or wrong IR length for any device in the chain is a frequent source of confusing errors. Pin count is a practical concern on small boards: JTAG's minimum four signal lines (with optional additional lines such as TRST) plus power and ground is manageable, but many space-constrained designs drop to SWD (two signals) when targeting Cortex-M parts. Tools and workflow comparisons for embedded development, including probe selection, are discussed in "Favorite Software AND Hardware Tools for Embedded Systems Development".
Discussed on EmbeddedRelated
Frequently asked
What is the difference between JTAG and SWD?
Both access the ARM CoreSight DAP for debug and programming on Cortex-M (and some Cortex-A/R) devices, but they differ in wiring. JTAG uses four signals (TDI, TDO, TCK, TMS, with TRST optionally present) and supports daisy-chaining multiple TAPs.
SWD uses only two signals (SWDIO, SWDCLK) and is a point-to-point protocol that does not support daisy-chaining multiple TAPs the way JTAG does. SWD is not defined in IEEE 1149.1 -- it is an ARM-proprietary protocol. For Cortex-M targets with limited pins or small connectors (e.g., a 10-pin or 5-pin Tag-Connect footprint), SWD is typically preferred. JTAG is necessary when chaining multiple devices or when working with parts that do not support SWD.
Can I use JTAG to program flash memory, or is it only for debugging?
Both. Most JTAG-capable debug probes and tools (
OpenOCD, J-Link software, Lauterbach TRACE32, vendor IDEs) include
flash programming algorithms that use the same JTAG connection to erase and write internal or external flash. On FPGAs and CPLDs, JTAG is a widely supported method for loading configuration bitstreams, though many devices also support other configuration interfaces such as passive serial,
SPI, or BPI. Programming and debug access share the same physical interface but are logically separate operations.
What does 'boundary scan' mean, and is it still useful?
Boundary scan is the original purpose of IEEE 1149.1. Shift
registers inserted at each I/O pin allow software to drive and sample pin states without the core running, enabling post-assembly tests for solder shorts, opens, and connectivity between ICs. On complex PCBs with JTAG-capable devices, boundary scan tools (e.g., XJTAG, Goepel) can verify board bring-up before firmware exists. In practice, many embedded developers use JTAG exclusively for debug and programming and never exercise the boundary-scan capability, but it remains valuable in production test and board verification workflows.
Why does my JTAG chain stop working when I add a second device?
JTAG daisy-chaining requires the host tool to know the exact number of devices in the chain and the instruction register (IR) length of each one. If a device is unrecognized, powered off, or has an incorrectly specified IR length, the shift chain breaks and all downstream TAPs become inaccessible. Check that every device in the chain is powered and that your tool's configuration (
OpenOCD config files, for example) lists each TAP with the correct IR length and IDCODE. Floating TDI or TDO lines are also a common culprit.
Do all microcontrollers support JTAG?
No. JTAG is common on ARM Cortex-A/R/M cores (STM32, NXP i.MX, Kinetis, SAM, nRF, etc.),
RISC-V parts, FPGAs, and DSPs. Many 8-bit and low-pin-count MCUs use vendor-specific alternatives: Microchip PIC and AVR devices often use ICSP; AVR also supports debugWIRE; STM8 uses SWIM; some Espressif ESP32 variants use JTAG but earlier ESP8266 parts did not. Always check the specific device's datasheet for supported debug and programming interfaces.
Differentiators vs similar concepts
JTAG is often compared to
SWD (Serial Wire Debug). SWD is an ARM-proprietary two-wire protocol that accesses the same CoreSight DAP as JTAG on Cortex-M/A/R targets, but it cannot daisy-chain multiple TAPs and is not defined in IEEE 1149.1. JTAG is also distinct from ISP/ICSP (In-System/In-Circuit Serial Programming) interfaces found on PIC and AVR devices: those are typically programming-only and lack the full debug register access that JTAG provides. Similarly, ST's SWIM (Single Wire Interface Module) on STM8 and Microchip's debugWIRE are single-wire, vendor-specific debug interfaces that serve a similar purpose to JTAG on their respective targets but are not IEEE 1149.1 compliant.
