MII (Media Independent Interface) is a standardized parallel interface defined in IEEE 802.3 that connects an Ethernet MAC (Medium Access Controller) to a PHY (Physical Layer device), decoupling the MAC from the specifics of the physical medium. It transfers nibble-wide (4-bit) data at 25 MHz to achieve 100 Mbps, or at 2.5 MHz for 10 Mbps, and includes a separate management serial bus called MDIO/MDC for PHY configuration and status.
In practice
MII appears in embedded designs whenever a microcontroller or SoC with an on-chip Ethernet MAC is connected to an external PHY chip. Common MCUs that expose an MII interface include the NXP LPC17xx/40xx series, STM32F2/F4/F7/H7 families, and various Microchip/Atmel SAM devices. The interface typically consists of separate transmit and receive data paths (TXD[3:0], RXD[3:0]), clock signals (TX_CLK, RX_CLK supplied by the PHY), and control/status signals (TX_EN, RX_DV, RX_ER, CRS, COL), though exact signal availability can vary by implementation and some signals are optional. Because the clocks are sourced from the PHY, the MAC must meet setup and hold timing relative to those clocks, which can require careful PCB layout at the signal rates involved.
MII has largely been superseded by RMII (Reduced MII) in newer designs. RMII cuts the pin count roughly in half by using a single 50 MHz reference clock (which can be driven by either the MAC side or an external oscillator, depending on the design) and reducing the data bus to 2 bits wide. Many modern Ethernet PHYs and MCU MAC peripherals support both MII and RMII and select between them via strapping pins or register configuration. GMII (Gigabit MII) is the 8-bit-wide, 125 MHz extension for 1000 Mbps, and RGMII is its reduced-pin-count variant commonly found on higher-end SoCs.
The MDIO/MDC management bus is a two-wire serial interface (MDC is a clock driven by the MAC; MDIO is bidirectional data) that is logically separate from the data path but is part of a complete MII-based Ethernet subsystem in virtually all standard MCU+PHY designs. It is used to read link status, configure auto-negotiation, set loopback modes, and access vendor-specific PHY registers. Accessing these registers is typically memory-mapped on the MAC side, and polling or interrupt-driven schemes are used to detect link-up/link-down events.
A common integration pitfall is clock domain management: the RX_CLK and TX_CLK pins are asynchronous to each other and to the MCU system clock, so DMA descriptors or FIFO handshakes in the MAC driver must correctly handle these boundaries. Another frequent issue is PHY reset sequencing -- the PHY reset pin must be held long enough (timing varies significantly by part, from microseconds to tens of milliseconds; consult the PHY datasheet) before MDIO accesses are attempted, and violating this can result in the PHY appearing present but non-functional.
Frequently asked
What is the difference between MII and RMII?
MII uses a 4-bit
data bus and separate TX/RX clocks (2.5 or 25 MHz) supplied by the PHY, requiring around 16 signals for the data path. RMII reduces this to a 2-bit data bus and a single 50 MHz reference clock (which the MAC or an external oscillator must provide), cutting the data-path pin count roughly in half. RMII is the more common choice in modern
MCU-based designs because of the lower pin and routing overhead.
Who supplies the clocks in an MII interface -- the MAC or the PHY?
In MII, both TX_CLK and RX_CLK are outputs of the PHY and inputs to the MAC. This is one of the key differences from RMII, where a single reference clock is typically provided by the MAC side or an external
crystal/oscillator to both the MAC and PHY.
What is MDIO and how does it relate to MII?
MDIO (Management Data Input/Output) is a two-wire serial bus (MDIO data line plus MDC clock line) defined alongside MII in IEEE 802.3. It is used to configure the PHY and read status
registers such as link speed, duplex mode, and fault conditions. It is separate from the data-plane signals but is part of a complete MII-based
Ethernet connection in virtually all standard implementations.
Can I use MII signals with a software or PIO-based MAC instead of a dedicated hardware MAC?
In principle yes, though it is demanding. The 25 MHz clock rate of 100 Mbps MII requires very tight timing that is difficult to meet in software on most MCUs. PIO-capable devices like the RP2040 have been used to implement simple MAC controllers (as explored in the blog post 'On hardware state machines: How to write a simple MAC controller using the RP2040 PIOs'), but such designs typically target 10 Mbps (2.5 MHz clock) where timing margins are more forgiving.
My Ethernet PHY is detected on MDIO but the link never comes up. What should I check first?
Common causes include: (1) PHY reset held too briefly -- reset timing varies by part (consult the datasheet), and many PHYs also require a stabilization delay after reset deassertion before MDIO is valid; (2) incorrect auto-negotiation configuration -- verify the advertised capabilities match the link partner; (3) TX_EN or RX_DV polarity/routing errors on the board; and (4) clock issues, such as the PHY's RX_CLK or TX_CLK not being routed to the MAC. Check the PHY's basic status register (MDIO register 1) for link status and the auto-negotiation complete bit as a first diagnostic step.
Differentiators vs similar concepts
MII is frequently confused with its derivatives. RMII (Reduced MII) halves the pin count by using a 2-bit bus and a single 50 MHz reference clock rather than MII's 4-bit bus with PHY-sourced TX/RX clocks. GMII (Gigabit MII) widens the
data bus to 8 bits and runs at 125 MHz for 1 Gbps; RGMII is its reduced-pin-count variant using
DDR signaling. SGMII is a serial variant widely used in SoC and switch contexts; SMII is an older serial variant with more limited adoption. All share the same MDIO/MDC management bus. The choice between these variants is usually dictated by the MAC peripheral built into the
MCU or SoC and the capabilities of the chosen PHY; MII itself is increasingly rare in new MCU designs, with RMII being the typical choice for 10/100 Mbps links.
