A parity bit is a single bit appended to a group of data bits whose value is set to make the total number of 1-bits in the group either always even (even parity) or always odd (odd parity). It is the simplest form of error detection, capable of flagging single-bit errors but not correcting them.
In practice
Parity bits appear commonly in asynchronous serial communication (UART), as well as in memory systems and other protocols. Most UART peripherals allow the parity mode to be configured as none, even, odd, mark (always 1), or space (always 0). In hardware UARTs, the parity bit is inserted automatically by the transmitter between the last data bit and the stop bit, and checked automatically by the receiver, which raises a parity error flag if a mismatch is detected; in software or bit-banged implementations it must be handled manually. Common frame configurations include 8N1 (8 data bits, no parity, 1 stop bit) and 8E1 or 8O1 when parity is enabled.
Parity detection only catches errors that flip an odd number of bits within the protected bits of the frame, assuming the error manifests as bit flips that parity can observe. A two-bit error in the same frame cancels out and goes undetected. For this reason, parity is considered weak error detection and is unsuitable for environments with burst noise or where data integrity is critical. In those cases, stronger schemes such as CRC are preferred, as discussed in "The CRC Wild Goose Chase: PPP Does What?!?!?!"
Beyond serial communication, parity bits appear in ECC RAM, where a more elaborate scheme uses multiple parity bits across a data word to both detect and correct single-bit errors (SECDED). Some safety-critical MCU designs, such as those targeting IEC 61508 or ISO 26262, include ECC on internal SRAM and flash to meet reliability requirements.
When implementing a software UART or bit-banged serial link (see "Bit-Banged Async Serial Output And Disciplined Engineering"), parity must be computed and inserted manually. The calculation is straightforward: XOR all data bits together to get the even-parity bit, then invert if odd parity is required.
Frequently asked
What is the difference between even and odd parity?
With even parity, the parity bit is set so the total count of 1-bits in the data plus parity is even. With odd parity, the total is always odd. Neither is universally superior; the choice must match between transmitter and receiver. Odd parity has the property that an all-zeros frame is an error condition (the count of 1-bits would be 0, which is even, not odd), which can make certain failure modes like a stuck-low line visible, though this is a niche consideration rather than a general advantage.
Can a parity bit correct errors, or only detect them?
A single parity bit can only detect errors, not correct them. It tells the receiver that something is wrong but provides no information about which bit flipped. Error correction requires additional redundancy, such as Hamming codes. Schemes like
CRC can support error recovery through retransmission at the protocol level, but do not correct errors by themselves.
Why does 8N1 dominate over 8E1 or 8O1 in most embedded UART use?
Parity provides weak protection and adds overhead (a 9th bit per frame, reducing effective throughput). Most embedded protocols layer their own framing and integrity checks on top of the raw byte stream, making per-byte parity redundant. Using all 8 data bits with no parity also keeps data byte values unambiguous, which simplifies protocol design.
How is a parity bit computed in software?
XOR all the data bits together. The result is the even-parity bit. For example, for the byte 0b10110001, XORing all bits gives 1 ^ 0 ^ 1 ^ 1 ^ 0 ^ 0 ^ 0 ^ 1 = 0, so the even-parity bit is 0 (four 1-bits, already even). For odd parity, invert the result. Many architectures also provide a dedicated parity instruction or a population-count (popcount) instruction that simplifies this calculation.
What is mark and space parity, and when is it used?
Mark parity forces the parity bit to always be 1; space parity forces it to always be 0. Neither provides any error detection. They exist mainly for backward compatibility with legacy systems that required a parity bit position in the frame but were not actually using it for checking. In modern designs these modes are rarely used.
Differentiators vs similar concepts
Parity is often compared to
CRC (cyclic redundancy check). Both are error-detection mechanisms appended to data, but they differ significantly in capability. A single parity bit covers one data word (typically 7 or 8 bits) and detects only odd-numbered bit errors within that word. A CRC covers an arbitrary-length message and can detect all single-bit errors, all double-bit errors (for common polynomials), all odd numbers of errors, and burst errors up to the width of the polynomial. CRC involves polynomial division (or a lookup table) rather than a simple XOR of bits, making it more computationally expensive but far more reliable. For anything beyond basic sanity-checking of individual
UART frames, CRC is the appropriate choice.
