PCI Express (PCIe) is a high-speed serial point-to-point interconnect standard used to connect processors, FPGAs, GPUs, storage controllers, and other peripherals via a switched, point-to-point fabric. It replaced the parallel PCI and PCI-X buses and is defined by the PCI-SIG specification, with generations ranging from PCIe 1.x (2.5 GT/s per lane) through PCIe 6.0 (64 GT/s per lane; note that PCIe 6.0 introduces PAM4 signaling and a FLIT-based encoding scheme, so per-lane usable throughput does not scale identically to prior NRZ generations).
In practice
PCIe appears in embedded systems primarily at the higher end of the performance spectrum: application processors, multicore SoCs, and FPGAs that need to move large amounts of data quickly. Typical use cases include attaching NVMe SSDs (which are native PCIe devices), GPUs or vision accelerators for machine-learning inference, Ethernet NICs, and custom FPGA-based coprocessor cards. Many automotive-grade SoCs (e.g., NXP i.MX 8, Renesas R-Car H3, Qualcomm SA8295P) include one or more PCIe root-complex controllers for exactly these workloads. Microcontroller-class devices (8-bit and most Cortex-M parts) do not implement PCIe; the interface is essentially absent below roughly the Cortex-A/R tier or high-end DSPs.
A PCIe link is organized into lanes, each a full-duplex pair of differential signals (TX+/TX- and RX+/RX-). Link widths of x1, x2, x4, x8, and x16 are defined; embedded designs most commonly use x1 or x4 to keep pin count and board complexity manageable. Each generation roughly doubles per-lane throughput: PCIe 3.0 delivers approximately 1 GB/s raw bandwidth per lane after 128b/130b encoding overhead, and PCIe 4.0 doubles that to roughly 2 GB/s per lane (these are close approximations; actual usable throughput is further reduced by protocol overhead, transaction mix, and implementation details). Actual system throughput depends on the root complex implementation in the SoC, DMA engine efficiency, and coherency overhead.
FPGAs are a particularly common host for PCIe in embedded co-design: Xilinx (now AMD) 7-series and UltraScale parts, Intel (Altera) Cyclone and Arria families, and Lattice ECP5 all include hard or soft PCIe IP blocks. As noted in "How FPGAs work, and why you'll buy one," FPGAs serve as flexible glue logic and high-bandwidth coprocessors, and PCIe is a primary interface for connecting them to a host CPU at speeds that USB or Ethernet cannot match.
Key pitfalls in embedded PCIe design include link training failures caused by reference clock quality or impedance mismatches, incorrect PCIe power sequencing (PERST# de-assertion timing relative to power rails), inadequate spread-spectrum clocking (SSC) handling, and underestimating the complexity of writing or porting a PCIe endpoint or root-complex driver on a custom Linux BSP. Signal integrity simulation and physical-layer compliance testing are typically required for any PCIe layout above x1 at Gen 2 speeds.
Frequently asked
What is a PCIe lane, and how does link width affect bandwidth?
A lane is one differential TX pair plus one differential RX pair, providing full-duplex communication. Link width (x1, x4, x8, x16) scales bandwidth linearly: a PCIe 3.0 x1 link yields roughly 1 GB/s in each direction, while a x4 link yields ~4 GB/s. Most embedded SoC PCIe controllers top out at x4 or x8, which is sufficient for NVMe storage or a moderately loaded
FPGA endpoint.
Is PCIe available on microcontrollers?
Rarely. PCIe is found mainly on application-processor SoCs and high-end DSPs, not on typical microcontrollers. A handful of industrial-grade 32-bit MCUs (e.g., some Renesas RZ/N and Infineon AURIX TC4x parts) include a PCIe controller, but it is the exception rather than the rule. For
MCU-to-PC communication,
UART,
USB, or
Ethernet are far more common choices.
What is the difference between a PCIe root complex and a PCIe endpoint?
The root complex is the host-side controller, typically integrated into a CPU or SoC, that initiates configuration cycles and manages the PCIe hierarchy. An endpoint is a peripheral device (NVMe drive, GPU,
FPGA card) that responds to requests from the root complex. In embedded co-design, an FPGA often acts as an endpoint connected to a CPU root complex, exposing memory-mapped BARs that the CPU driver accesses via
DMA or
MMIO.
How does PCIe handle backward compatibility across generations?
PCIe is electrically and mechanically backward compatible within the same slot width. During link training, the device and its root port negotiate the highest PCIe generation that both ends support and that the interconnect path can sustain; a Gen 4 device connected to a Gen 3 root port will train at Gen 3 speeds. Software and driver interfaces are also backward compatible across generations, which simplifies board bring-up when mixing devices from different PCIe generations.
What are the main signal-integrity challenges when routing PCIe on an embedded board?
Each differential pair must be length-matched within a lane (intra-pair skew typically under 5 mil) and inter-lane skew must be kept within the limits specified by the PCIe PHY and device datasheets (refer to per-spec values rather than relying on a single rule of thumb, as limits tighten with each generation). Trace impedance is targeted at 85 ohm differential. AC coupling
capacitors (100 nF typical) are required on every TX lane. Reference clock jitter must meet PCIe PHY specifications (typically 300 ps peak-to-peak for Gen 1/2, tighter for Gen 3+). Power delivery to the PCIe device must be stable before PERST# is de-asserted, or link training will fail.
Differentiators vs similar concepts
PCIe is often contrasted with its predecessor, parallel PCI/PCI-X, and with other high-speed embedded interconnects. PCI used a shared parallel bus (32-bit at 33 or 66 MHz, up to 533 MB/s for PCI-X 133); PCIe replaced it with switched, point-to-point serial links that scale by adding lanes. Compared to
USB 3.x, PCIe offers lower
latency, higher raw throughput, and a memory-mapped programming model suited to
DMA-heavy peripherals, but requires far more complex PCB routing and a dedicated root-complex controller in the SoC. Compared to CXL (Compute Express Link), which is built on top of the PCIe physical layer, PCIe provides
general-purpose I/O while CXL adds
cache-coherent memory expansion semantics. Within embedded interconnects, PCIe competes with
Ethernet-based fabrics (1/10/25 GbE) for board-to-board links; PCIe has lower latency and CPU overhead for local expansion but does not extend beyond a single board without PCIe-over-cable or switching infrastructure.
