A Power-on Reset (POR) is a hardware circuit that holds a microcontroller or SoC in reset until the supply voltage has risen to a level at which the device can operate reliably. It prevents the CPU from executing code from an undefined state during power ramp-up.
In practice
Most MCUs and SoCs include a POR circuit on-chip, though some designs rely on external supervisory ICs or power-management ICs instead. When VDD crosses a defined threshold (commonly somewhere between 1.5 V and 2.8 V depending on the device), the POR circuit releases the reset line; the processor then begins executing from its reset vector, though on some devices additional stabilization delays or boot ROM behavior may intervene before application code runs. Until that threshold is reached, RAM and most internal state is indeterminate -- registers and peripherals that lack defined reset states may also be unreliable -- and the POR ensures code does not start running in that window. On STM32 parts, for example, the POR threshold is typically around 1.7 V for 3.3 V-powered devices, specified in the electrical characteristics section of the datasheet.
POR is distinct from the broader reset system on most MCUs, which also includes sources such as brown-out reset (BOR), watchdog reset, software reset, and external pin reset. The POR fires only on initial power application; subsequent resets from other sources generally follow different paths, though on some devices these reset sources share closely related logic and the distinction may be less clear-cut. Many MCUs expose a reset-cause register (e.g., STM32 RCC_CSR, MSP430 SYSRSTIV, AVR MCUSR) that lets firmware distinguish a POR from other reset types at boot, though not all devices offer this -- some provide only limited or sticky flags, and others may clear flags early in startup -- which is useful for deciding whether to initialize RAM, restore state from non-volatile memory, or log a fault.
Slow power supply ramp rates can expose weaknesses in POR design. If VDD rises very slowly (tens of milliseconds or more), some on-chip POR circuits may not assert reset long enough, or the threshold voltage may be crossed and re-crossed if the supply is noisy. External supervisory ICs -- such as those in the Maxim MAX6xxx or Texas Instruments TPS3xxx families (though not every part in these families offers the same feature set) -- can provide tighter, more configurable thresholds and longer reset pulse widths than many on-chip POR circuits. The blog post "How to Design Reliable Reset Circuits for Embedded Microcontrollers" covers this trade-off in detail.
On systems that sequence multiple supply rails (common on application processors and FPGAs), POR should be coordinated across rails. A core rail may come up before an I/O rail, and asserting reset until all rails are stable prevents bus contention or latch-up, though some systems use other sequencing mechanisms or are designed to tolerate partial-power states. The boot sequence posts for ARM-based systems ("Boot Sequence for an ARM based embedded system" and "Boot sequence for an ARM based embedded system -2") discuss how POR fits into the broader power-up and boot flow on more complex SoCs.
Discussed on EmbeddedRelated
Frequently asked
What is the difference between POR and brown-out reset (BOR)?
POR fires once when supply voltage first rises above a threshold from an unpowered state.
BOR monitors the supply continuously after power-up and asserts reset if voltage later drops below a (usually configurable) threshold. On many MCUs the BOR threshold is set higher than the POR threshold so that momentary supply dips during operation are caught before the device enters an unreliable operating region.
Can I rely solely on the on-chip POR circuit, or do I need an external supervisor?
For many designs the on-chip POR is sufficient, especially when the supply ramps quickly and cleanly. External supervisory ICs are worth considering when the supply ramp is slow or non-monotonic, when the application requires a tighter or adjustable threshold, when a longer guaranteed reset pulse width is needed, or when multiple rails must be sequenced. The exact capability of the on-chip POR varies significantly between vendors and even between device families from the same vendor, so check the datasheet carefully.
How does firmware detect that a POR occurred rather than some other reset?
Most MCUs latch the reset source in a status register that firmware can read early in the boot sequence. Examples include RCC_CSR (STM32), SYSRSTIV (MSP430), MCUSR (AVR), and RSTC_SR (SAM). The POR flag in that register is typically set only on a true power-on event. Firmware should read and then clear this register early in startup before any other reset source can overwrite it.
Does a POR guarantee that RAM contents are zeroed?
Not in general. POR guarantees the CPU starts executing from a known state (the reset vector), but
RAM cells power up to indeterminate values. Zeroing BSS and initializing data sections is the responsibility of the C runtime startup code (typically crt0 or equivalent), which runs before main(). Relying on RAM being zero after a POR without that initialization step is a common source of hard-to-reproduce bugs.
Why might a board fail to start reliably even with an on-chip POR?
Common causes include a supply that ramps too slowly for the on-chip POR to assert correctly, a non-monotonic ramp (the voltage briefly dips or oscillates near the threshold), bulk capacitance that causes the supply to cross the POR threshold more than once, or a POR threshold that is too close to the device's minimum operating voltage. Adding an external reset supervisor IC with a defined threshold and a minimum reset pulse width (often 100 ms or more) resolves most of these issues. Decoupling and PCB layout also matter, as covered in "The Least Interesting Circuit in the World".
Differentiators vs similar concepts
POR is often conflated with
brown-out reset (BOR) and with external reset pins. POR is specifically the circuit that detects the initial rise of supply voltage from zero and releases reset once a safe operating level is reached. BOR is a separate (though related) circuit that monitors supply voltage during normal operation and resets the device if it sags below a threshold. An external reset pin (NRST, RESET, MCLR) provides a manual or supervisory reset path but is independent of supply voltage sensing. Many MCUs incorporate all three mechanisms, and their interaction -- including which source wins and what the reset-cause register reports -- is defined per device in the datasheet.
