QSPI (Quad Serial Peripheral Interface) is an extended form of SPI that uses four data lines (IO0–IO3) instead of the standard single MOSI/MISO pair, enabling up to 4 bits per clock cycle during the data phase and roughly quadrupling theoretical data throughput at the same clock frequency compared to single-line SPI. In practice, the data lines are bidirectional but direction is determined per phase: during any given data phase all active lines carry data in the same direction, though the specific line roles vary by command and device. It is most commonly used to interface microcontrollers and SoCs with external flash memory and PSRAM devices.
In practice
In most embedded designs, QSPI appears as the interface to an external NOR flash chip — for example, a Winbond W25Q series or Micron MT25Q part connected to an STM32, ESP32, or Kinetis MCU. The bus operates in one of several modes: single (standard SPI), dual (2 data lines), or quad (4 data lines). The quad mode only applies to the data phase; the command and address phases are typically still sent on a single line, though some devices support full quad addressing as well. Many MCU peripherals that implement QSPI also support an execute-in-place (XIP) mode, where the controller maps the flash into the MCU's address space so code or read-only data can be fetched directly without explicit read commands in firmware.
A common pitfall is conflating the electrical interface with the peripheral's operating mode. The MCU-side QSPI peripheral must be configured to match the specific flash device's quad-enable bit, dummy cycle count, and command opcodes exactly. Getting these wrong typically results in corrupted reads or a non-responsive flash — bugs that can be hard to distinguish from a wiring problem. Many vendors provide HAL drivers or CMSIS-Pack flash algorithms that handle this configuration, but porting between flash devices from different manufacturers often requires updating these parameters manually.
Clock frequency limits are another practical concern. While the QSPI peripheral on parts like the STM32H7 can be clocked up to 110 MHz (yielding up to 440 Mbps on four lines), the actual achievable speed is constrained by PCB trace length, the flash device's timing specs, and the sample-delay calibration supported by the controller. On high-speed designs, the hold time and data valid window narrow significantly, and many designs must reduce clock frequency or adjust sampling delay to achieve reliable operation.
When the QSPI peripheral is used in memory-mapped (XIP) mode, cache coherency and write-through behavior become important. Writing to the flash device requires temporarily disabling the memory-mapped mode, sending erase and program commands, then re-enabling XIP — a sequence that must be executed entirely from internal SRAM or cache to avoid a fetch from the flash device while it is being written.
Discussed on EmbeddedRelated
Frequently asked
What is the difference between QSPI and standard SPI?
Standard
SPI uses one dedicated output line (MOSI) and one dedicated input line (MISO), transferring 1 bit per clock per direction. QSPI repurposes those lines and adds two more, creating four data lines (IO0–IO3). During a read or write data phase, all four lines carry data in the same direction, giving up to 4 bits per clock cycle and roughly 4x the throughput at equivalent clock rates.
Can I connect a QSPI flash to a standard SPI peripheral?
Yes, with limitations. Most QSPI
flash devices (Winbond W25Q, Micron MT25Q, ISSI IS25LP, etc.) power up in single-SPI-compatible mode and respond to standard
SPI commands on that one data line. You can read and write them this way, but you forgo the quad-speed data transfer. You also cannot use XIP/memory-mapped mode through a standard SPI peripheral.
What is execute-in-place (XIP) mode and which hardware supports it?
In XIP mode, the QSPI controller continuously handles read transactions autonomously, and the
flash's address range is mapped into the
MCU's memory map. The CPU can fetch instructions and data directly from flash as if it were internal memory. XIP is supported by dedicated QSPI/OSPI controllers on parts such as the STM32F4/F7/H7 (via QUADSPI peripheral), ESP32 (which boots from XIP by default), and NXP i.MX RT series (FlexSPI). Standard
SPI peripherals do not support XIP.
Why does my QSPI flash work in single-SPI mode but not in quad mode?
Quad mode on most
flash devices is gated behind a quad-enable (QE) bit in the flash's status register. Until that bit is set, the IO2 and IO3 pins are used for alternate functions (WP# and HOLD#) and will interfere with quad transfers. The QE bit must be written via a standard
SPI WRSR (Write Status Register) command before switching to quad mode. Additionally, the dummy cycle count and command opcodes for quad read (e.g., 0xEB for Fast Read Quad I/O on Winbond parts) must match between the
MCU peripheral configuration and the flash datasheet exactly.
Is QSPI the same as OSPI or OctoSPI?
No. OctoSPI (used by STM32 in their OCTOSPI peripheral, and by some other vendors) extends the concept to eight data lines (IO0–IO7), doubling throughput again compared to quad mode. Some OctoSPI peripherals also support HyperBus, an interface used by HyperFlash and HyperRAM devices. Most external
NOR flash and PSRAM parts available today still use quad (4-line) interfaces, so OctoSPI peripherals typically operate in quad-mode compatibility when connected to standard QSPI
flash.
Differentiators vs similar concepts
QSPI is often confused with standard
SPI, Dual SPI, and OctoSPI, which form a family of progressively wider variants of the same basic protocol. Standard SPI uses 1 data line in each direction (half-duplex in practice for
flash); Dual SPI uses 2 data lines; QSPI uses 4; OctoSPI (as implemented in STM32's OCTOSPI peripheral and others) uses 8. All share the same clocked, chip-select-based framing, though vendor peripherals and flash devices vary in opcode sets, address and data phase widths, and command behavior, so these width increments are not a single unified standard across all manufacturers. QSPI is also sometimes confused with the "QSPI" designation used in some Texas Instruments
DSP documentation, where the term refers to a queued SPI controller — a mechanism for queuing SPI transfers — rather than a quad-data-line bus; the two uses of the acronym describe fundamentally different things.
